Z87000 Datasheet, PDF (23/50 Pages) Zilog, Inc. – Spread Spectrum Controllers

Zilog
Tx signal
4-bit DAC
NCO
Z87000/Z87L00
Spread Spectrum Controllers
Tx Buffer
1
Spectral
Shaping
Figure 3. Modulator Block Diagram
Transmit 4-Bit DAC
The transmit DAC clocks one new NCO value out of the
Z87000 every 8.192 MHz period. Only the 10.7 MHz alias
frequency component of the transmit signal (2.508 + 8.192
MHz image) is filtered, amplified and upconverted to the
900 MHz ISM band by the companion RF module.
Event Trigger Block
The event trigger block is responsible for scheduling the
different events happening at the bit and frame levels. The
event trigger block receives input from the frame counters
as well as the register interface of the DSP core processor.
The event trigger schedules the following events:
s Start of the 4 ms frame: a synthesizer load enable pulse
is issued on the SYLE pin
s Power-up of the modulator section and transmission of
the frame on handset and base station
s Use of the bit inversion as function of mode
s Power-up of the demodulator section and reception of
the frame on handset and base station
s Control of RFTX and RFRX output pins, to be used as
TDD control signals switching the antenna as well as
transmitter and receiver chains on the RF module
s Control of RFEON pin, to be used as general on/off
switch on the RF module
s Control of the Z87000 sleep mode
4-Bit DAC for Setting Transmit Power Level
In order to save battery life, the Z87000 only transmits the
amount of RF power needed to reach the remote receiver
with a sufficient SNR margin. The on-board transmit power
4-bit DAC provides 4 different voltage levels to the power
amplifier in the RF module for that purpose. This DAC is di-
rectly controlled by the Z87000 software through an output
register.
8-Bit ADC for Sampling the Received Signal
Strength Indicator (RSSI)
RSSI information is typically generated from the last stage
of the RF receiver. The RSSI is sampled once per frame
by the 8-bit ADC and used by the Z87000 software to com-
pute the necessary Transmit Power Level voltages.
DSP Core Processor
A DSP core processor constitutes the heart of the Z87000.
The DSP runs the application software which performs the
following functions:
s Register initialization
s Implementation of high-level phone features; control of
phone user interface (keypad, Led, etc.)
s Control of the Z87010 ADPCM Processor
s Control of the phone line interface
s Ring detection by DSP processing
s Communication protocol between handset and base
station supporting voice and signalling channels
s Control of the RF synthesizer and adaptive frequency
hopping algorithm
s Control of the RF power and adaptive power algorithm
s Control of the demodulator (bit synchronizer loop filter,
AFC bias estimate filtering)
s Control of the modulator (carrier frequency) and
adaptive frequency alignment
s Signalling between base and handset to support above
features
The DSP core is characterized by an efficient hardware ar-
chitecture that allows fast arithmetic operations such as
multiplication, addition, subtraction and multiply-accumu-
late of two 16-bit operands. Most instructions are executed
in one clock cycle.
DS96WRL0501
PRELIMINARY
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