Z87000 Datasheet, PDF (38/50 Pages) Zilog, Inc. – Spread Spectrum Controllers

Z87000/Z87L00
Spread Spectrum Controllers
Zilog
REGISTER DESCRIPTION (Continued)
Table 14. Bank 3 Register Description
SSPSTATE
Field
Bank 3
Bit Position
EXT2
R/W Data Description
TX_ENABLE
SYNC_SEARCH_WORD
SYNC_SEARCH_MODE
HOP_ENABLE
SYNC_ACQ_CLEAR
FRAME_START_CLEAR
SLEEP_WAKE
MULTIPLEX_SWITCH
GO_TO_SLEEP
-----a----------
------9---------
-------87-------
---------6------
----------5-----
-----------4----
------------3---
-------------21-
---------------0
R/W 0*
1
R/W 0*
1
R/W 00*
01
10
11
R/W 0
1
R
W 1->0
R
W 1->0
R/W 0
1
R/W 00*
01
10
11
R
W 0->1
Global enable for all transmit functions
Transmitter disabled
Transmitter enabled
Controls the word searched for in search mode
Search for UW pattern (Unique Word)
Search for SYNC_D pattern
Controls the search mode (and frame synchronization)
No search
Window search (<= UW_LOCATION & WINDOW_SIZE)
Full search (during whole frame)
Not used
Enables transmission of the hop pulse on SYLE pin
Hop pulse disabled
Hop pulse enabled
Clears the SYNC_ACQ_IND flag.
Returns last value written
A transition from 1 to 0 clears the flag
Clears the FRAME_START_IND flag
Returns last value written
A transition from 1 to 0 clears the flag
Enable bit for entering sleep mode
Wake mode only
Sleep mode can be activated by GO_TO_SLEEP command
Controls operation of the transceiver
SMUX (bit inversion and ADPCM Processor access disabled)
STMUX (bit inv. enabled; ADPCM Proc. access disabled)
Reserved
TMUX (bit inversion and ADPCM Processor access enabled)
Command bit to place the Z87000 in sleep mode
Returns last value written
A transition from 0 to 1 causes Z87000 sleep mode
Notes:
1. DBP_STOP_CLOCK. When this bit is set to 1, the ADPCM Processor clock (CLKOUT) is stopped within two clock periods. When
this bit is set to 0, the ADPCM Processor clock restarts within two clock periods; in every case, the ADPCM Processor clock min-
imum specifications for high time and low time are respected.
2. BSYNC_GAIN. Changes to this bit take effect immediately.
BIAS_ENABLE. This bit is a global enable for the Automatic Frequency Control. When the bit is set, the AFC hardware updates
the current BIAS_ERROR_DATA during specific time windows, controlled by the event trigger hardware and suitable for a good
operation of the AFC. When the bit is reset, the AFC operation is suspended. However, the current BIAS_ERROR_DATA, result-
ing from previous bias estimations, can still be used to bias the downconverter NCO. Changes to the BIAS_ENABLE bit take effect
at the beginning of the frame following the change.
3. TX_ENABLE. Global control for all system transmit functions, including RFTX pin control (timing set by the RFTX_PWR_ON/OFF
register fields) and power to the modulator and NCO (timing set by MOD_PWR_ON and the wake/sleep modes).
4. Changes to this bit take effect immediately.
5. HOP_ENABLE. Changes to this bit take effect immediately.
6. SLEEP_WAKE. This bit must be set to enable the core to put itself to sleep via the GO_TO_SLEEP command. The SLEEP_WAKE
bit must be reset to prevent the core to fall back to sleep after it is awaken by one of the Port 0 Wake-up pins when the sleep period
has not expired. If the bit is not reset, the core will fall right back to sleep when the wake-up input is de-asserted (note that by
design, a wake-up input has a minimum of 10 ms duration, to allow the software enough time to safely reset the SLEEP_WAKE
bit).
7. SYNC_AQC_CLEAR. This bit must be set to “1” again after every “clear” operation to allow for the next “clear”.
8. FRAME_START_CLEAR. This bit must be set to “1” again after every “clear” operation to allow for the next ?“clear”.
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PRELIMINARY
DS96WRL0501