Z87000 Datasheet, PDF (39/50 Pages) Zilog, Inc. – Spread Spectrum Controllers

Zilog
Z87000/Z87L00
Spread Spectrum Controllers
Table 15. Bank 3 Register Description
SSPSTATUS
Bank 3
EXT3
Field
Bit Position
R/W Data
Description
1
FRAME_COUNTER fedcba987------
Current frame counter value
R 00h First value at beginning of frame (0)
...
173h Last value at end of frame (371)
... Illegal values
W
No effect
RESERVED
---------65---- R
Returns 0
W
No effect
HAND_BASE_SEL -----------4---
Reflects status of Handset/Base select pin (HBSW)
R
0 Base (HBSW = 0)
1 Handset (HBSW = 1)
W
No effect
SYNC_ACQ_IND
------------3--
Indicates detection of a Sync word (UW or SYNC_D
depending on SYNC_SEARCH_WORD search mode)
R
0 No sync word detected
W
1 Sync word detected
No effect
FRAME_START_IND ------------2--
Indicates start of a new frame
R
0 No start of new frame (1 written to
1 FRAME_START_CLR)
W
New frame started
No effect
RESERVED
-------------10 R
Returns 0
W
No effect
Notes:
FRAME_COUNTER. Read the double-buffered current value of the Frame Counter.
On the handset, a single frame counter is used to clock transmit and receive events.
On the base station, the transmit frame counter value is returned
GPIO0DIR
Field
DIRECTION0
Table 16. Bank 3 Register Description
Bit 3
Bit Position
fedcba9876543210
EXT4
R/W
R/W
Data Description
Independent control of Port 0 pin direction
..0. Sets pin in input mode
..1. Sets pin in output mode
Table 17. Bank 3 Register Description
GPIO0DATA
Field
Bank 3
Bit Position
EXT5
R/W Data
Description
DATA0
fedcba9876543210
Access to Port 0 data
R XXXXh Reads pin values
W XXXXh Writes output pin values
Notes:
DATA0. The read value returns the actual pin values and does not depend on the pin directions
(i.e. for output pins, the output value is returned unless a contention occurs).
DS96WRL0501
PRELIMINARY
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