Z87000 Datasheet, PDF (19/50 Pages) Zilog, Inc. – Spread Spectrum Controllers

Zilog
Z87000/Z87L00
Spread Spectrum Controllers
PIN FUNCTIONS
V_DD. Digital power supply.
GND. Digital ground.
AV_DD. Analog power supply.
CLKOUT (output). Clock output for external ADPCM pro-
cessor.
1
CODCLK (output). Clock output for external voice CO-
DEC.
AGND. Analog ground.
/RESETB (input, active low). Reset signal.
V_REF (analog reference). This signal is the reference volt-
age used by the high speed analog comparator to sample
the RX input signal.
VXADD[2..0] (input). Address bus controlled by external
ADPCM processor. The Z87000 acts as peripheral of the
Z87010 ADPCM processor.
RX (analog input). This is the RX IF receive signal from
the RF module, input to the analog comparator and FSK
demodulator. It is internally biased to the V_REF DC voltage.
The IF signal from the RF module should be AC coupled
to the RX pin.
VXDATA[7..0](input/output). Read/write data bus con-
trolled by external Z87010 ADPCM processor.
VXSTRB (input). Data strobe signal for the VXDATA bus,
controlled by external Z87010.
TX (analog output). This is the IF transmit signal to the RF
module, output from the FSK modulator and transmit 4-bit
D/A converter.
RXON (output; active high or low programmable). This
pin reflects the programming of the demodulator turn-on
time.
VXRWB (input). Read/write control for the VXDATA bus,
controlled by external Z87010.
VXRDYB (output, active low). Ready control for the VX-
DATA bus. This signal is driven high (de-asserted) by the
Z87000 to insert wait states in the Z87010 ADPCM proces-
sor accesses.
RFRX (output; active high or low programmable). Control
for the receive switch on the RF module. Active during re-
ceive periods.
RFTX (output; active high or low programmable). Control
for the transmit switch on the RF module. Active during
transmit periods.
RFEON (output; active high or low programmable).
On/off control for the RF module. Active (on) during wake
periods. Inactive (off) during sleep periods on the handset.
RSSI (analog input). Receive signal strength indicator
from RF module, input to the RSSI 8-bit ADC.
PWLV (analog output). Power level control for RF module,
output from the transmit power 4-bit DAC.
SYLE (output). RF synthesizer load enable: latches new
frequency hopping control word of external RF synthesiz-
er. Programmable polarity.
ANT[1..0] (output). Control for optional antenna diversity
on the RF module.
MCLK (input). Master clock input.
TEST (input, active high). Main test mode control. Must be
set to GND.
HBSW (input with internal pull-up). Control for hand-
set/base configuration. Must be driven high or not connect-
ed for handset, low for base.
P0[15..0] (input/output). General-purpose I/O port. Direc-
tion is bit-programmable. Pins P0[3..0],when configured in
input mode, can also be individually programmed as wake-
up pins for the Z87000 (wake-up active low; signal internal-
ly debounced and synchronized to the bit clock).
P0 0
P0 1
P0 2
P0 3
WAKEUP0
WAKEUP1
WAKEUP2
WAKEUP3
P1[15..0] (input/output).General-purpose I/O port. Direc-
tion is bit-programmable. Pins P114 and P115, when con-
figured in input mode, also behave as individually
maskable interrupt pins for the core processor (positive
edge-triggered).
P1 14
P1 15
INT0
INT2
DS96WRL0501
PRELIMINARY
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