Z87000 Datasheet, PDF (34/50 Pages) Zilog, Inc. – Spread Spectrum Controllers

Z87000/Z87L00
Spread Spectrum Controllers
Zilog
REGISTER DESCRIPTION
The Z87000 DSP core processor has four banks of eight
registers mapped in the core processor’s “external regis-
ter” space, as summarized in the following table.
Table 10. Register Summary
BANK ADDRESS
REGISTER
Bank 3 EXT0 CONFIG1
EXT1 CONFIG2
EXT2 SSPSTATE
EXT3 SSPSTATUS
Bank 2
Bank 1
EXT4
EXT5
EXT6
EXT7
EXT0
EXT1
EXT2
EXT3
EXT4
EXT5
EXT6
EXT7
EXT0
EXT1
GPIO0DIR
GPIO0DATA
GPIO1DIR
GPIO1DATA
VP_INOUT
RX_CONTROL
BIAS_ERROR
RSSI
CORE_BIAS
MOD_PWR_CTRL
DEMOD_PWR_CTRL
RFTX_PWR_CTRL
RATE_BUF_ADDR
RATE_BUF_DATA
Bank 0
EXT2
EXT3
EXT4
EXT5
EXT6
EXT7
EXT0
EXT1
EXT2
EXT3
EXT4
EXT5
EXT6
EXT7
BIT_SYNC
RESERVED
RESERVED
RESERVED
CONTROL
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
INT_SYM_ERR0
RFRX_PWR_CTRL
READ DESCRIPTION
WRITE DESCRIPTION TABLE #
Clock Dividers, Use Core Bias, Table 25
SYLE polarity, search window
size, Bias Threshold
Remaining Sleep time
ANT0/1 control, Sleep Period Table 26
Stop VP clock, Absent gain, Bias Enable, Tx Enable, Sync
Search control, Hop Enable, Frame Start control, Multiplex
control, Sleep mode control
Table 27
Frame Counter, Handset/Base,
Sync Search control, Frame
Start control
Table 28
General-Purpose I/O port 0 direction control
Table 29
General-Purpose I/O port 0 data
Table 30
General-Purpose I/O port 1 direction control
Table 31
General-Purpose I/O port 1 data
Table 32
ADPCM Processor Status ADPCM Processor Command Table 33
SNR estimate
UW location
Table 34
FCW value
Table 35
8-bit ADC data (RSSI)
Table 36
Core Bias data
Table 37
MOD_PWR control
Table 38
RXON, RFEON pin control Table 39
RFTX pin control
Table 40
Rate Buffer address
Table 41
Re Rate Buffer data
Tx Rate Buffer data, control Table 42
data
Bit Sync monitoring
Bit Sync control
Table 43
Table 44
Table 44
Table 44
INT, WAKEUP pin control, 4-bit DAC data (PWLV)
Table 45
Table 46
Table 47
Table 47
Table 47
Table 47
Table 47
Table 47
Bit Sync monitoring
Table 47
RFRX, RXON pin control Table 49
1-34
PRELIMINARY
DS96WRL0501