Z87000 Datasheet, PDF (26/50 Pages) Zilog, Inc. – Spread Spectrum Controllers

Z87000/Z87L00
Spread Spectrum Controllers
Zilog
OPERATION (Continued)
Modulator Control
The MOD_FREQ fields specify the carrier center frequen-
cy (should be programmed to 2.508 MHz) and deviation for
the FSK signal (should be programmed to ± 32.58 kHz). In
addition, wave shaping is performed on bit transitions, in
order to satisfy FCC regulations. Up to four different inter-
mediate deviation values are programmable for each of
the two FSK states. The MOD_FREQ fields are program-
mable in units of 62.5 Hz.
Bit Synchronizer
The bit synchronizer circuit is an implementation of the
Data-Transition-Tracking Loop (DTTL), best described in
“Telecommunications Systems Engineering”, by W. Lind-
sey and M. Simon (Dover 1973; oh. 9 p. 442). Its operation
is summarized in the following block diagram.
Table 1. AFC and Modulator Control Fields
Field
BIAS_THRESHOLD
BIAS_ENABLE
BIAS_ERROR_DATA
CORE_BIAS_DATA
Register
CONFIG1
SSPSTATE
BIAS_ERROR
CORE_BIAS
Bank EXT
3 EXT0
3 EXT2
2 EXT2
2 EXT4
Discriminator
Output
In-phase
Matched
Filter
Mid-phase
Matched
Filter
Recovered
Bit clock
Transition
Detection
Error
Magnitude
Clock
Generator
Signed
Error
Loop Filter
division “by 1”
“by 64”
first order
INT_SYM_ERR0
INT_SYM_ERR1
SECOND_ORDER
BSYNC_GAIN
Figure 6. Bit Synchronizer Loop and Processor Control
DSP Core
Processor
1-26
PRELIMINARY
DS96WRL0501