Z87000 Datasheet, PDF (37/50 Pages) Zilog, Inc. – Spread Spectrum Controllers

Zilog
Z87000/Z87L00
Spread Spectrum Controllers
Table 14. Bank 3 Register Description
SSPSTATE
Bank 3
EXT2
Field
Bit Position
R/W Data Description
1
SW_SYLE
f---------------
Controls accelerated synthesizer programming after sleep
R/W 0* Not Active
1
Active
STOP_CODCLK
-e--------------
Inhibits toggling of codec clock output during sleep
R/W 0* CODCLK is free running
1
CODCLK is frozen high
DBP_STOP_CLOCK --d-------------
Controls toggling of CLKOUT output pin (clock for ADPCM
Processor).
R/W 0* CLKOUT is free running
1
CLKOUT is frozen high
BSYNC_GAIN
---c------------
Selects gain for first order loop of the bit synchronizer
R/W 0* Nominal gain
1
Gain divided by 64
BIAS_ENABLE
----b-----------
Controls closed-loop AFC circuit
R/W 0* No new bias estimation is performed (latest estimate used)
1
Enables BIAS_ERROR_DATA updates
TX_ENABLE
-----a----------
Global enable for all transmit functions
R/W 0* Transmitter disabled
1
Transmitter enabled
SYNC_SEARCH_WORD ------9---------
Controls the word searched for in search mode
R/W 0* Search for UW pattern (Unique Word)
1
Search for SYNC_D pattern
SYNC_SEARCH_MODE -------87-------
Controls the search mode (and frame synchronization)
R/W 00* No search
01 Window search (<= UW_LOCATION & WINDOW_SIZE)
10 Full search (during whole frame)
11 Not used
HOP_ENABLE
---------6------
Enables transmission of the hop pulse on SYLE pin
R/W 0
Hop pulse disabled
1
Hop pulse enabled
SYNC_ACQ_CLEAR ----------5-----
Clears the SYNC_ACQ_IND flag.
R
Returns last value written
W 1->0 A transition from 1 to 0 clears the flag
FRAME_START_CLEAR -----------4----
Clears the FRAME_START_IND flag
R
Returns last value written
W 1->0 A transition from 1 to 0 clears the flag
SLEEP_WAKE
------------3---
Enable bit for entering sleep mode
R/W 0
Wake mode only
1
Sleep mode can be activated by GO_TO_SLEEP
command
MULTIPLEX_SWITCH -------------21-
Controls operation of the transceiver
R/W 00* SMUX (bit inversion and ADPCM Processor access
01 disabled)
10 STMUX (bit inv. enabled; ADPCM Proc. access disabled)
11 Reserved
TMUX (bit inversion and ADPCM Processor access
enabled)
GO_TO_SLEEP
--------------0
Command bit to place the Z87000 in sleep mode
R
Returns last value written
W 0->1 A transition from 0 to 1 causes Z87000 sleep mode
DS96WRL0501
PRELIMINARY
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