Z87000 Datasheet, PDF (32/50 Pages) Zilog, Inc. – Spread Spectrum Controllers

Z87000/Z87L00
Spread Spectrum Controllers
Zilog
OPERATION (Continued)
The operation of the receive rate buffer is identical. The
Z87000 core processor must set the nibble address in
RX_BUF_ADDR, then read the nibble from
RX_BUF_DATA. If the RX_AUTO_INCREMENT bit is set,
the read address is automatically incriminated (modulo 36
= number of nibbles in rate buffer) after each data read.
This allows the DSP core to read successive nibbles with-
out resetting the address each time.
Through its register interface, the Z87000 also controls
which rate buffer addresses the Z87010 ADPCM Proces-
sor can access. The nibble addresses are contained in the
TX_BUF_VP_ADDR and RX_BUF_VP_ADDR register
fields. After the Z87010 writes or reads a nibble to or from
transmit or receive rate buffer, the corresponding
“VP_ADDR” is automatically incriminated (modulo 36) to
the next accessible address. The locations of accessible
addresses are individually controlled by the Z87000 in the
three TX_RX_NIBBLE_MARKER register fields. A marker
bit equal to “1” enables the Z87010 to access the corre-
sponding address; a bit equal to “0” causes the Z87010’s
read or write access to skip to the next nibble that has a
marker bit equal to “1”.
Demodulator
Modulator
RX_BUF_DATA
RX RATE BUFFER
Z87000
Address
Decoder
TX RATE BUFFER
RX_BUF_VP_ADDR
TX_RX_NIBBLE_
MARKER
TX_BUF_VP_ADDR
TX_BUF_DATA
RX_BUF_ADDR
RX_AUTO_INCR.
TX_BUF_ADDR
TX_AUTO_INCR.
DSP Core
Processor
ADPCM Proc.
Interface
Data
Addr
Ctrl
VP_COMMAND
VP_STATUS
Figure 9. Rate Buffers Access and ADPCM Processor Interface
1-32
PRELIMINARY
DS96WRL0501