Z87000 Datasheet, PDF (40/50 Pages) Zilog, Inc. – Spread Spectrum Controllers

Z87000/Z87L00
Spread Spectrum Controllers
REGISTER DESCRIPTION (Continued)
GPIO1DIR
Field
DIRECTION1
Table 18. Bank 3 Register Description
Bank 3
Bit Position
fedcba9876543210
EXT6
R/W
R/W
Data
Description
Independent control of Port 1 pin direction
..0. Pin in input mode
..1. Pin in output mode
Zilog
Table 19. Bank 3 Register Description
GPIO1DATA
Field
Bank 3
Bit Position
EXT7
R/W Data
Description
DATA1
fedcba9876543210
Access to Port 1 data
R XXXXh Reads pin values
W XXXXh Writes output pin values
Notes:
DATA1. The read value returns the actual pin values and does not depend on the pin directions
(i.e. for output pins, the output value is returned unless a contention occurs)
Bank 2 Registers
VP_INOUT
Field
RESERVED
VP_STATUS
VP_COMMAND
Table 20. Bank 2 Register Description
Bank 2
Bit Position
fedcba98--------
--------76543210
--------76543210
EXT0
R/W
R
W
R
W
Data
Description
Returns 0
No effect
Access to ADPCM Processor’s Command/Status
mailbox
XXh Reads Status byte from ADPCM Processor
Access to ADPCM Processor’s Command/Status
mailbox
XXh Writes Command byte to ADPCM Processor
Table 21. Bank 2 Register Description
RX_CONTROL
Field
Bank 2
Bit Position
EXT1
R/W Data
Description
SNR_ESTIMATE
fedcba9876543210
Access to channel measurement (SNR) estimate
Returns the SNR value
R XXXXh
UW_LOCATION
-------876543210
Location of the Unique Word
W XXXXh Initializes the value that the receive frame counter
is set to on detection of the Unique Word
Notes:
SNR_ESTIMATE. This value is updated every frame. It should be read by
the software during the frequency hopping guard time of the next frame.
1-40
PRELIMINARY
DS96WRL0501