Z87000 Datasheet, PDF (44/50 Pages) Zilog, Inc. – Spread Spectrum Controllers

Z87000/Z87L00
Spread Spectrum Controllers
Zilog
REGISTER DESCRIPTION (Continued)
Bank 1 Registers
Table 28. Bank 1 Register Description
RATE_BUF_ADDR
File
Bank 1
Bit Position
EXT0
R/W
RESERVED
f-------------- R
W
RX_AUTO_INCREMENT -e-------------
R
W
RX_BUF_ADDR
--dcba98--------
R
W
RESERVED
--------7------- R
W
TX_AUTO_INCREMENT ---------6------
R
W
TX_BUF_ADDR
----------543210
R
W
Data
Description
Returns 0
No effect
Controls the auto-increment feature of the Rx rate
buffer
0 Returns 0
1 Disables auto-increment
Enables auto-increment
Access to Rx rate buffer address
Returns 0
00h Address 0
... ...
23h Address 23h = 35
... Illegal
Returns 0
No effect
Controls the auto-increment feature of the Tx rate
buffer
0 Returns 0
1 Disables auto-increment
Enables auto-increment
Access to Tx rate buffer address
Returns 0
00h Address 0
... ...
23h Address 23h = 35
24h Tx/Rx rate buffer address for ADPCM Processor
25h accesses
26h Tx/Rx Nibble Marker bits [15..0]
27h Tx/Rx Nibble Marker bits [31..16]
28h Tx/Rx Nibble Marker bits [35..32]
29h MOD_FREQ_DEV 0
2Ah MOD_FREQ_DEV 1
2Bh MOD_FREQ_DEV 2
2Ch MOD_FREQ_DEV 3
2Dh MOD_FREQ_DEV 4
2Eh MOD_FREQ_DEV 5
2Fh MOD_FREQ_DEV 6
30h MOD_FREQ_DEV 7
31h MOD_FREQ_DEV 8
32h MOD_FREQ_DEV 9
... MOD_CENTER_FREQ
Illegal
1-44
PRELIMINARY
DS96WRL0501