Z87000 Datasheet, PDF (45/50 Pages) Zilog, Inc. – Spread Spectrum Controllers

Zilog
Z87000/Z87L00
Spread Spectrum Controllers
Table 29. Bank 1 Register Description
RATE_BUF_DATA
Bank 1
EXT1
Field
Bit Position
R/W Data
Description
1
RX_BUF_DATA
------------3210
Access to the Rx rate buffer data
R
Xh Reads value at current RX_BUF_ADDR
address (0 to 23h)
TX_BUF_DATA
------------3210
Access to the Tx rate buffer data
W XXXXh Writes value at current TX_BUF_ADDR address
(0 to 23h)
TX_BUF_VP_ADDR
--dcba98--------
Sets the initialization value of the Tx rate buffer
address used for ADPCM Processor accesses
W XXh Writes initialization value (TX_BUF_ADDR
address= 24h)
RX_BUF_VP_ADDR
----------543210
Sets the initialization value of the Rx rate buffer
address used for ADPCM Processor accesses
W XXh Writes initialization value (TX_BUF_ADDR
address= 24h)
TX_RX_NIBBLE_MARKER fedcba9876543210
Sets the Nibble Marker register for Tx and Rx
rate buffer accesses by ADPCM Processor
W XXXXh Write nibble marker value (TX_BUF_ADDR=
25h to 27h)
MOD_FREQ
fedcba9876543210
Access to modulator settings
W XXXXh Writes modulator setting value
(TX_BUF_ADDR=28h to 32h)
Note:
The meaning and address for any RATE_BUF_DATA is set in the RATE_BUF_ADDR register.
MOD_FREQ. The unit for center frequency and frequency deviation words is 62.5 Hz.
These words are encoded as 2’s complement numbers.
The meaning and address for any RATE_BUF_DATA is set in the RATE_BUF_ADDR register.
MOD_FREQ. The unit for center frequency and frequency deviation words is 62.5 Hz.
These words are encoded as 2’s complement numbers.
Table 30. Bank 1 Register Description
BIT_SYNC
Field
INT_SYM_ERR1
SECOND_ORDER
Bank 1
Bit Position
EXT2
R/W Data
Description
fedcba9876543210
R
fedcba9876543210
W
Read access to the integrated symbol error from the bit
synchronizer’s second order loop
XXXXh Reads error data bits [23..8] (bits [7..0] are in bank 0,
EXT6)
Write access to the bit synchronizer’s second-order loop
XXXXh Writes second order loop’s 16-bit value
RESERVED
Field
RESERVED
DS96WRL0501
Table 31. Bank 1 Register Description
Bank 1
Bit Position
fedcba9876543210
EXT3
EXT4
EXT5R/W Data
Description
R
Returns 0
W 0000h Must be left alone or written to 0000h (or
unpredictable results may occur)
PRELIMINARY
1-45