Z87000 Datasheet, PDF (29/50 Pages) Zilog, Inc. – Spread Spectrum Controllers

Zilog
Z87000/Z87L00
Spread Spectrum Controllers
The following table summarizes the fields allowing control In addition to the SYLE signal, the interface to the most RF
of frame synchronization and basic frame timing.
synthesizers includes two more input lines, “data” and
Table 3. Frame Synchronizer Control Fields
Field
SYNC_SEARCH-MODE
SYNC_SEARCH_WORD
UW_LOCATION
WINDOW_SIZE
Register
SSPSTATE
SSPSTATE
RX_CONTROL
CONFIG1
Bank Ext
3 EXT2
3 EXT2
2 EXT1
3 EXT0
1 ^{“clock”, for serial programming of the data values defining}
the RF channel. In order to allow interfacing to various
popular synthesizers, the Z87000 does not have dedicated
clock and data lines with fixed timing. Instead, two general
I/O pins from ports P0 and P1 can be controlled in software
by the DSP core to realize any particular interface timing.
This flexibility is made possible by the high speed, single-
cycle architecture of the DSP core.
MULTIPLEX_SWITCH
SYNC_ACQ_IND
SSPSTATE
SSPSTATUS
3 EXT2
3 EXT3
The transmitter control includes a global enable signal for
all transmit functions: TX_ENABLE. The transmission start
SYNC_ACQ_CLEAR
FRAME_COUNTER
FS_INT_ENABLE
SSPSTATE
SSPSTATUS
CONTROL
3 EXT2
3 EXT3
1 EXT6
is controlled by the MOD_PWR_ON field. On the base sta-
tion, the value programmed in MOD_PWR_ON is refer-
enced to the transmit frame counter.
FRAME_START_IND
FRAME_START_CLEAR
SYNC_SEARCH-MODE
SSPSTATUS
SSPSTATE
SSPSTATE
3 EXT3
3 EXT2
3 EXT2
Two additional fields, RFTX_PWR_ON and
RFTX_PWR_OFF, define the duty cycle of the RFTX out-
put pin. On the base station, these fields are referenced to
the transmit frame counter. The RFTX_POLARITY bit de-
RF Interface
Several control fields are available in the Z87000 register
set to control the timing and polarity of the RF module in-
terface signals.
A first field, RFEON_POLARITY, controls the polarity of
the RFEON pin. This pin should be used to control the
power of the RF module. It is asserted by the Z87000 when
the RF module is in use, and de-asserted in sleep mode.
The sleep mode is used by the handset to save battery life
when no phone call is in process (See “Sleep mode” on
page 21).
fines the polarity of the RFTX pin. This pin can be used to
control the transmit section and power amplifier of the ex-
ternal RF module.
On the receive side, two fields define the internal timing of
the receiver. The start of reception is controlled by the
DEMOD_PWR_ON field. Stop of reception (and receiver
power down) is controlled by the DEMOD_PWR_OFF
field. On the base station, these fields are referenced to
the receive frame counter. The RXON output pin follows
the timing defined by the DEMOD_PWR_ON and OFF
fields.
The SYLE pin (Synthesizer Load Enable), which carries a
“load enable” pulse that tells an external RF synthesizer to
generate the next RF channel, is controlled by two fields.
The HOP_ENABLE field is a global enable signal for the
SYLE signals. The SYLE_POLARITY field defines the po-
larity of the SYLE pin. The system designer should ensure
that the leading edge of the SYLE pulse triggers channel
Two additional fields, RFRX_PWR_ON and
RFRX_PWR_OFF, define the duty cycle of the RFRX out-
put pin. On the base station, these fields are referenced to
the TRANSMIT (!) frame counter. The RFRX_POLARITY
bit defines the polarity of the RFRX and RXON pins. The
RFRX pin can be used to control the receive section of the
external RF module.
hopping.
DS96WRL0501
PRELIMINARY
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