Z87000 Datasheet, PDF(33/50 Page) Zilog, Inc. – Spread Spectrum Controllers

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

Z87000 Datasheet, PDF (33/50 Pages) Zilog, Inc. – Spread Spectrum Controllers

◁

Zilog

Z87000/Z87L00

Spread Spectrum Controllers

Table 7. Data and Control Access to Rate Buffers

General-Purpose I/O Ports

Field

RX_AUTO_INCREMENT

RX_BUF_ADDR

TX_AUTO_INCREMENT

TX_BUF_ADDR

RX_BUF_DATA

RATE_BUF_ADDR

RATE_BUF_DATA

Bank Next

1 EXT0

The Z87000 includes two general-purpose input/output

1 ports, P0 and P1, of 16 bit each. The direction of each bit

is independently programmable by setting the register

fields DIRECTION0 and DIRECTION1. Then, the software

can access the input and output values by accessing

DATA0 and DATA1.

TX_BUF_DATA

RX_BUF_VP_ADDR

TX_BUF_VP_ADDR

TX_RX_NIBBLE_MARKER

RATE_BUF_ADDR

RATE_BUF_DATA

1 EXT1

Two pins of port P1 (pins 14 and 15), when configured in

input mode, also behave as interrupt pins for the core pro-

cessor. The software can enable or disable each interrupt

by setting the INTERRUPT_0_ENABLE and

INTERRUPT_2_ENABLE fields. The interrupts are posi-

tive edge-triggered.

Additional Features

Power Control

Number

Interrupt

Number

DSP Interrupt

Vector

The Z87000 features several means of measuring and

controlling power levels. One input pin (RSSI) connects an

external âreceive signal strength indicatorâ to a half flash 8-

bit ADC in the Z87000. This ADC is sampled once per

frame during the receive portion of the TDD cycle. The

RSSI value can be accessed in software in the

RSSI_DATA register field. With external multiplexing, the

8-bit ADC can be used for additional purposes.

P1 14

P1 15

INT0

INT2

3FFFh

3FFDh

Table 9. General-Purpose I/O Ports

Field

The RSSI data is used by the software to implement adap-

tive power control. In order to determine whether the RSSI

information is made of signal or noise, the Z87000 includes

logic to measure the signal-to-noise ratio (SNR) of the re-

ceive signal. This SNR value is available at the end of ev-

ery frame in the SNR_ESTIMATE register field. It is also

used by the adaptive frequency hopping algorithm to de-

termine and avoid the noisy channels.

Finally, a 4-bit DAC (resistive ladder) is provided to control

RF power output level. The DAC is under software control

through register field TX_PWR_DAC_DATA.

DIRECTION0

GPI00DIR

EXT4

DATA0

GPI00DATA

EXT5

DIRECTION1

GPI0IDIR

EXT6

DATA1

GPI0IDATA

EXT7

INTERRUPT_0_ENABLE CONTROL

EXT6

INTERRUPT_1_ENABLE CONTROL

EXT6

Four pins of port P0 (pins 0 to 3), when configured in input

mode, can also be individually programmed as wake-up

pins for the Z87000 (See âSleep modeâ on page 21).

Table 8. Power Control

Field

RSSI_DATA

SNR_ESTIMATE

TX_PWR_DAC_DATA

RSSI_DATA

SNR_ESTIMATE

RSSI

RX_CONTROL

CONTROL

RSSI

RX_CONTROL

Bank Ext

2 EXT3

2 EXT1

1 EXT6

2 EXT3

DS96WRL0501

PRELIMINARY

1-33

▷