Z87000 Datasheet, PDF (46/50 Pages) Zilog, Inc. – Spread Spectrum Controllers

Z87000/Z87L00
Spread Spectrum Controllers
Zilog
REGISTER DESCRIPTION (Continued)
Table 32. Bank 1 Register Description
CONTROL
Field
Bank 1
Bit Position
EXT6
R/W Data
Description
RESERVED
fedcb----------- R
W
Returns 0
No effect
FS_INT_ENABLE
-----a----------
R/W
Controls frame start interrupt (INT1)
0* Disables frame start interrupt
1 Enables frame start interrupt
INTERRUPT_0_ENABLE ------9---------
R/W
Controls interrupt 0 (INT0 on P114)
0* Disables interrupt 0
1 Enables interrupt 0
INTERRUPT_2_ENABLE -------8--------
R/W
Controls interrupt 2 (INT2 on P115)
0* Disables interrupt 2
1 Enables interrupt 2
P0_WAKEUP_ENABLE
--------7654----
Controls wake-up pins (P0[3..0])
R/W 0000* Disables all wake-up pins
1xxx Enables P03 as wake-up pin (if in input mode)
x1xx Enables P02 as wake-up pin (if in input mode)
xx1x Enables P01 as wake-up pin (if in input mode)
xxx1 Enables P00 as wake-up pin (if in input mode)
TX_PWR_DAC_DATA
------------3210
R/W
Access to Tx power 4-bit DAC output data
Xh Sets output value
Note:
P0_WAKEUP_ENABLE. When enabled, pins P0[3..0] are active low wake-up pins for the Z87000 sleep mode.
The input signal is internally debounced and synchronized to the bit clock. It is internally given a minimum duration of one bit to
allow the software to exit sleep mode safely.
RESERVED
Field
RESERVED
Table 33. Bank 1 Register Description
Bank 1
Bit Position
EXT7
R/W
fedcba9876543210 R
W
Data
Returns 0
No effect
Description
1-46
PRELIMINARY
DS96WRL0501