Z87000 Datasheet, PDF (25/50 Pages) Zilog, Inc. – Spread Spectrum Controllers

Zilog
Z87000/Z87L00
Spread Spectrum Controllers
OPERATION
Automatic Frequency Control Loop
(Receiver) and Modulator
1 ^{The accumulated bias, available in BIAS_ERROR_DATA,}
can be used directly to correct the NCO frequency. Alter-
nately, the estimated bias can be read by the DSP, further
AFC Loop
processed, and written to the CORE_BIAS_DATA field.
The AFC loop consists of a bias estimator block, which de-
termines frequency offsets in the incoming signal, an
adder, to add this bias to the 460 kHz frequency control
word driving the NCO, and various interface points to the
The DSP controls which value is used by setting the
USE_CORE_BIAS field. The selected value is added to
the 460 kHz signal which downconverts the receive IF sig-
nal.
DSP core processor. In particular, the DSP can read the
bias estimate data and substitute its own calculated bias
value to the NCO.
The CORE_BIAS_DATA and BIAS_ERROR_DATA are
two’s complement numbers in units of 125 Hz.
The bias estimator accumulates the discriminator output
values (image of instantaneous frequency) that exceed a
programmable threshold (BIAS_THRESHOLD). The pro-
cessor can freeze the bias calculation any time by reset-
ting the BIAS_ENABLE control bit.
In addition to correcting the difference in clock frequencies
on the receiver using the AFC loop, a Z87000-base system
can also modify the frequency of the remote transmit IF
signals. The software has access to this frequency through
the MOD_FREQ register fields.
Rx signal
460 kHz
+ bias
Second down-
convertor,
Discriminator
Discriminator
Output
Bias estimator
“0”
BIAS_THRESHOLD
BIAS_ENABLE
Downconverter
NCO and bias
adder
BIAS_ERROR_DATA
CORE_BIAS_DATA
USE_CORE_BIAS
DSP Core
Processor
Figure 5. AFC Loop and Processor Control
DS96WRL0501
PRELIMINARY
1-25