Z87000 Datasheet, PDF (15/50 Pages) Zilog, Inc. – Spread Spectrum Controllers

Zilog
Z87000/Z87L00
Spread Spectrum Controllers
ADPCM Processor Interface
READ CYCLES refer to data transfers from the Z87000 to
The Z87000 is a peripheral device for the ADPCM Proces- ^{the ADPCM Processor.}
sor. The interface from the Z87000 perspective is com-
posed of an input address bus, a bidirectional data bus,
WRITE CYCLES refer to data transfers from the ADPCM
Processor to the Z87000.
1
strobe and read/write input control signals and a
ready/wait output control signal.
Signal Name
VXADD[2..0]
VXDATA[7..0]
VXSTRB
VXRWB
VXRDYB
Table 11. Read Cycles
Function
Address Bus
Data Bus
Strobe Control Signal
Read/Write Control Signal
Ready Control Signal
Direction
ADPCM Proc. to Z87000
Bidirectional
ADPCM Proc. to Z87000
ADPCM Proc. to Z87000
Z87000 to ADPCM Proc.
Table 12. Write Cycles
No.
Symbol
Parameter
Min
Max
Units
8
TsAS Address, Read/Write setup time before Strobe falls
10
ns
9
ThSA Address, Read/Write hold time after Strobe rises
3
ns
10
TaDrS Data read access time after Strobe falls
30 (1)
ns
11
ThDrS Data read hold time after Strobe rises
8.5
40 (2)
ns
12
TwS
Strobe pulse width
20
13
TsDwS Data write setup time before Strobe rises
10
ns
14
ThDwS Data write hold time after Strobe rises
3
ns
15
TaDrRY Data read valid before Ready falls
22
ns
16
TdSRY Strobe high after Ready falls
0
ns
Notes:
1. Requires wait state on ADPCM Processor read cycles
2. Requires no write cycle directly following read cycle on ADPCM Processor
DS96WRL0501
PRELIMINARY
1-15