Z87000 Datasheet, PDF (24/50 Pages) Zilog, Inc. – Spread Spectrum Controllers

Z87000/Z87L00
Spread Spectrum Controllers
FUNCTIONAL DESCRIPTION (Continued)
Zilog
The DSP core is operated at the internal speed of 8.192
MHz. It has an internal RAM memory of 512 16-bit words
divided in two banks. Six register pointers provide circular
buffering capabilities and dual operand fetching. Three
vectored interrupts are complemented by a six-level stack.
One interrupt is used by the transceiver, while the two re-
maining vectors are mapped into port P1. In the phone
system, one of these interrupts is customarily reserved for
the Z87010 ADPCM Processor. The other interrupt can be
used for custom purposes.
The Z87000 has a (12K+128) x 16-bit internal ROM includ-
ing 4 words for interrupt and reset vectors. The ROM is
mapped at addresses 0000h to 2FFFh, 3F80h to 3FFFh,
as shown in Figure 13.
3FFFh
3F80h
128w ROM
3000h
2FFFh
Int. Vector 0
Int. Vector 1
Int. Vector 2
Reset Vector
3FFFh
3FFEh
3FFDh
3FFCh
12K
USER ROM
Z87010 Interface
In addition to providing clock signals to the Z87010 proces-
sor, the Z87000 interfaces to the Z87010 through two dif-
ferent paths:
s A command/status interface
s A data interface
The command/status interface consists of two dual-port
registers accessible by both Z87000 and Z87010 DSP
core processors. On the Z87000 side, the registers are
mapped into the DSP core processor’s register interface.
To allow access by the Z87010, the internal command/sta-
tus registers can also be decoded on the pinto of the
Z87000. Arbitration logic resolves access contentions.
The data interface allows the Z87010 processor direct ac-
cess to the Z87000’s receive and transmit rate buffers. The
rate buffers are decoded on the pin to of the Z87000, and
dedicated voice processor interface logic handles the ad-
dressing within the rate buffers.
The physical interface between Z87000 and Z87010 con-
sists of an 8-bit data bus, a 3-bit address bus and control
signals, as summarized in the following:
VXDATA[7.0]
VXADD[2.0]
VXSTRB
VXRWB
VXRDYB
Data bus
Address bus
Data Strobe
Read/Write Control
Read Control
0000h
Figure 4. ROM Mapping
Two 16-Bit General-Purpose I/O Ports
Two 16-bit general-purpose I/O ports are directly accessi-
ble by the DSP core. These input and output pins are typ-
ically used for:
s Implementation of the phone’s user interface (keypad,
LED, optional display, etc.)
s Control of phone line interface (on/off hook, ring detect)
s Control of battery charging and detection of low battery
conditions
s Implementation of additional features for customizing of
the phone
This bus is controlled by the Z87010. Although in the sys-
tem the Z87010 is enslaved to the Z87000 master, at the
physical level the Z87000 acts as a peripheral of the
Z87010.
The mapping of the command status and data interfaces
from the Z87010 side is given below.
Address
Interface (VXADD [2.0])
Transmit
1
rate buffer
Receive
1
rate buffer
Command
0
Status
0
Read
/Write
W
Data
(VXDATA[7.0])
----3210
R ----3210
R 76543210
W 76543210
1-24
PRELIMINARY
DS96WRL0501