Z87000 Datasheet, PDF (36/50 Pages) Zilog, Inc. – Spread Spectrum Controllers

Z87000/Z87L00
Spread Spectrum Controllers
REGISTER DESCRIPTION (Continued)
Zilog
Table 13. Bank 3 Register EXT1
Config 2
Field
Bank 3
Bit Position
ANTENNA_SW_DEFEAT f---------------
ANTENNA_SW_OFFSET -edcba98--------
EXT1
R/W Data
Description
Controls optional antenna switching
(ANT0 and ANT1 pins)
R
Returns 0
W 0 Enables antenna switching
1 Disables antenna switching
Controls antenna switching time advancement
Returns 0
R
Offset in number of 2.048 MHz clock cycles
W xXh (<108)
SLEEP_PERIOD
--------76543210
SLEEP_REMAINING --------76543210
W 00h Programs sleep duration in sleep mode Illegal
01h Sleep period=1 frame (4 ms)
•••
FFh Sleep period = 255 frames (1.020s)
Returns value of sleep counter when sleep mode
is interrupted by a “wake” signal
R 00h Normal expiration of sleep counter
01h One frame left before normal expiration
•••
FFh 255 frames left before normal expiration
Notes:
1. SLEEP_PERIOD. In sleep mode, the RFEON pin is active. Changes to this bit take effect immediately.
2. SLEEP_REMAINING. A non-zero value indicates that the Z87000 was awakened by a key press activating one of the wake-up
pins on port 0. In this case, the processor should immediately reset the SLEEP_WAKE field in SSPSTATE to prevent the pro-
cess from going back to sleep when the user key press ceases.
1-36
PRELIMINARY
DS96WRL0501