DS568 Datasheet, PDF (9/22 Pages) Xilinx, Inc – LogiCORE IP XPS LL FIFO

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DS568 March 1, 2011
Product Specification
LogiCORE IP XPS LL FIFO (v1.02a)
BEGIN xps_ll_temac
PARAMETER INSTANCE = xps_ll_temac_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x81200000
PARAMETER C_HIGHADDR = 0x8120ffff
PARAMETER C_BUS2CORE_CLK_RATIO = 2
PARAMETER C_TEMAC_TYPE = 0
PARAMETER C_PHY_TYPE = 1
PARAMETER C_TEMAC1_ENABLED = 1
BUS_INTERFACE SPLB = plb_v46_0
BUS_INTERFACE LLINK0 = LLINK0
BUS_INTERFACE LLINK1 = LLINK1
PORT SPLB_Clk = CLK_100MHz
PORT Core_Clk = CLK_50MHz
PORT REFCLK = CLK_200MHz
PORT TemacPhy_RST_n = temacPhy_RST_n
PORT GTX_CLK_0 = clk_125mhz
PORT LlinkTemac0_CLK = CLK_100MHz
PORT LlinkTemac1_CLK = CLK_100MHz
PORT GMII_TXD_0 = int_GMII_TXD_0
PORT GMII_TX_EN_0 = int_GMII_TX_EN_0
PORT GMII_TX_ER_0 = int_GMII_TX_ER_0
PORT GMII_TX_CLK_0 = int_GMII_TX_CLK_0
PORT GMII_RXD_0 = int_GMII_RXD_0
PORT GMII_RX_DV_0 = int_GMII_RX_DV_0
PORT GMII_RX_ER_0 = int_GMII_RX_ER_0
PORT GMII_RX_CLK_0 = int_GMII_RX_CLK_0
PORT MII_TX_CLK_0 = int_MII_TX_CLK_0
PORT MDC_0 = int_MDC_0
PORT MDIO_0 = int_MDIO_0
PORT GMII_TXD_1 = int_GMII_TXD_1
PORT GMII_TX_EN_1 = int_GMII_TX_EN_1
PORT GMII_TX_ER_1 = int_GMII_TX_ER_1
PORT GMII_TX_CLK_1 = int_GMII_TX_CLK_1
PORT GMII_RXD_1 = int_GMII_RXD_1
PORT GMII_RX_DV_1 = int_GMII_RX_DV_1
PORT GMII_RX_ER_1 = int_GMII_RX_ER_1
PORT GMII_RX_CLK_1 = int_GMII_RX_CLK_1
PORT MII_TX_CLK_1 = int_MII_TX_CLK_1
PORT MDC_1 = int_MDC_1
PORT MDIO_1 = int_MDIO_1
PORT TemacIntc0_Irpt = int_TemacIntc0_Irpt
PORT TemacIntc1_Irpt = int_TemacIntc1_Irpt
END
BEGIN xps_ll_fifo
PARAMETER INSTANCE = xps_ll_fifo_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x81400000
PARAMETER C_HIGHADDR = 0x8140ffff
BUS_INTERFACE SPLB = plb_v46_0
BUS_INTERFACE LLINK = LLINK1
PORT PLB_Clk = CLK_100MHz
PORT IP2INTC_Irpt = int_FifoInc1_Irpt
END
BEGIN xps_ll_fifo
PARAMETER INSTANCE = xps_ll_fifo_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x81300000
PARAMETER C_HIGHADDR = 0x8130ffff
BUS_INTERFACE SPLB = plb_v46_0
BUS_INTERFACE LLINK = LLINK0
PORT PLB_Clk = CLK_100MHz
PORT IP2INTC_Irpt = int_FifoInc0_Irpt
END
DS568_03_101708
Figure 3: EDK MHS File Code Segment
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