DS568 Datasheet, PDF (21/22 Pages) Xilinx, Inc – LogiCORE IP XPS LL FIFO

LogiCORE IP XPS LL FIFO (v1.02a)
Device Utilization and Performance Benchmarks
Because the XPS LL FIFO is a module that will be used with other design pieces in the FPGA, the utilization and
timing numbers reported in this section are estimates only. As the XPS LL FIFO core is combined with other pieces
of the FPGA design, the utilization of FPGA resources and timing of the XPS LL FIFO core design will vary from the
results reported here. The XPS LL FIFO core benchmarks are shown in Figure 17 for a Virtex5-LXT FPGA.
Table 17: XPS LL FIFO FPGA Performance and Resource Utilization Benchmarks
Parameter Values
C_SPLB_P2P
0
Slices
496
Device Resources
Slice Flip- Flops
577
LUTs
995
F_MAX (MHz)
F_MAX
170
1
473
581
1002
166
Reference Documents
1. DS562 PLBv46 Slave Burst
2. LocalLink Interface Specification (SP006)
3. EDK Processor IP Reference Guide
4. IBM CoreConnect 128-Bit Processor Local Bus, Architectural Specification Version 4.6
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that
are not defined in the documentation, if customized beyond that allowed in the product documentation, or if
changes are made to any section of the design labeled DO NOT MODIFY.
Ordering Information
This Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx ISE Design Suite Embedded
Edition software under the terms of the Xilinx End User License. The core is generated using the Xilinx ISE
Embedded Edition software (EDK).
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page.
For information on pricing and availability of other Xilinx LogiCORE modules and software, please contact your
local Xilinx sales representative.
Reference Documents
1. DS562 PLBv46 Slave Burst
2. LocalLink Interface Specification (SP006)
3. EDK Processor IP Reference Guide
4. IBM CoreConnect 128-Bit Processor Local Bus, Architectural Specification Version 4.6
DS568 March 1, 2011
www.xilinx.com
21
Product Specification