DS568 Datasheet, PDF (1/22 Pages) Xilinx, Inc – LogiCORE IP XPS LL FIFO

DS568 March 1, 2011
LogiCORE IP XPS LL FIFO
(v1.02a)
Product Specification
Introduction
The LogiCORE™ IP XPS LL FIFO is a soft IP core
designed for Xilinx FPGAs.
This core allows memory mapped access to a LocalLink
interface. The core can be used to interface to the XPS
LL TEMAC without the need to use DMA. Other uses
include interfacing to the LocalLink interfaces on
PLBv46 PCIe and PLBv46 PCI.
The principal operation of this core allows the write or
read of data packets to or from a device without any
concern over the LocalLink interface. The LocalLink
interface is transparent to the user.
Features
• 32-bit PLBv46 slave interface with point to point
optimizations
• Independent internal 2 Kb TX and RX data FIFOs
• Full duplex operation
• Provides interrupts for many error and status
conditions
LogiCORE IP Facts Table
Core Specifics
Supported
Device Family
Spartan-3A/-3A DSP, Spartan-3, Spartan-3E,
Automotive Spartan-3/-3E/-3A DSP, Spartan-6,
Virtex-4/-4Q/-4QV, Virtex-5/-5FX, Virtex-6/-6CX
Supported User
Interfaces
LocalLink
Resources
Configuration
LUTs
FFs
DSP
Slices
Block
RAMs
Config1
996 Min 577 Min 473 Min
1002 Max 581 Max 496 Max
2 Min
2 Max
Provided with Core
Documentation
Product Specification
Design Files
VHDL
Example Design
Not Provided
Test Bench
Not Provided
Constraints File
UCF
Simulation
Model
VHDL
Tested Design Tools
Design Entry
Tools
EDK 11.4 or later
Simulation
ModelSim PE/SE 6.4b or later
Synthesis Tools
XST
Support
Provided by Xilinx, Inc.
© Copyright 2008-2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United
States and other countries. PCIe is the trademark of PCI-SIG and used uner license. All other trademarks are the property of their respective owners.
DS568 March 1, 2011
www.xilinx.com
1
Product Specification