DS568 Datasheet, PDF (12/22 Pages) Xilinx, Inc – LogiCORE IP XPS LL FIFO

LogiCORE IP XPS LL FIFO (v1.02a)
Table 5: Interrupt Status Register Bit Definitions (Cont’d)
Bit(s)
Name
Core Access
Reset
Value
Description
Transmit Complete. Indicates that at least one transmit has completed.
4
TC
Read/Clear on
Write of "1"
0
"0" = No interrupt pending.
"1" = Interrupt pending.
Receive Complete. Indicates that at least one successful receive has
completed and that the receive packet data and packet data length is
available. This signal is not set for unsuccessful receives. This interrupt may
5
RC
Read/Clear on
Write of "1"
0
represent more than one packet received so it is important to check the
receive data FIFO occupancy value to determine if additional receive
packets are ready to be processed.
"0" = No interrupt pending.
"1" = Interrupt pending.
Transmit Size Error. Transmit Size Error. This interrupt is generated if the
number of 32-bit words (including partial words in the count) written to the
transmit data FIFO does not match the value written to the transmit length
register (bytes) divided by 4 and rounded up to the higher integer value for
6
TSE
Read/Clear on
Write of "1"
0
trailing byte fractions. Interrupts occur only for mismatch of word count
(including partial words). Interrupts do not occur due to mismatch of byte
count. A reset of the transmit logic is required to recover.
"0" = No interrupt pending.
"1" = Interrupt pending.
Transmit Reset Complete. This interrupt indicates that a reset of the
7
TRC
Read/Clear on
Write of "1"
0
transmit logic has completed.
"0" = No interrupt pending.
"1" = Interrupt pending.
Receive Reset Complete. This interrupt indicates that a reset of the receive
8
RRC
Read/Clear on
Write of "1"
0
logic has completed.
"0" = No interrupt pending.
"1" = Interrupt pending.
9-31 Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will
always return all zeros.
The Interrupt Enable Register, Figure 6, determines which interrupt sources in the Interrupt Status Register are
allowed to generate interrupts.
Figure Top x-ref 6
RPUEE
RPUREE
TCE
TSEE RRCE
0123456789
31
RPOREE
RCE TRCE
TPOEE
Reserved
Figure 6: Interrupt Enable Register (offset 0x4)
DS568_06_101708
DS568 March 1, 2011
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Product Specification