DS568 Datasheet, PDF (10/22 Pages) Xilinx, Inc – LogiCORE IP XPS LL FIFO

LogiCORE IP XPS LL FIFO (v1.02a)
Registers Definition
The registers in Table 4 are contained in the XPS LL FIFO.
Table 4: XPS LL FIFO Registers
Register Name
Interrupt Status Register (ISR)
Interrupt Enable Register (IER))
PLB Address
C_BASEADDR + 0x0
C_BASEADDR + 0x4
Access
Read/Clear on Write⁽¹⁾
Read/Write
Transmit data FIFO reset (TDFR)
Transmit data FIFO Vacancy (TDFV)
Transmit data FIFO 32bit wide data write port (TDFD)
Transmit Length FIFO (TLF)
C_BASEADDR + 0x8
C_BASEADDR + 0xC
C_BASEADDR + 0x10
C_BASEADDR + 0x14
Write⁽²⁾
Read
Write
Write
Receive data FIFO reset (RDFR)
Receive data FIFO Occupancy (RDFO)
Receive data FIFO 32bit wide data read port (RDFD)
Receive Length FIFO (RLF)
C_BASEADDR + 0x18
C_BASEADDR + 0x1C
C_BASEADDR + 0x20
C_BASEADDR + 0x24
Write⁽²⁾
Read
Read
Read
LocalLink reset (LLR)
Reserved
C_BASEADDR + 0x28
C_BASEADDR + 0x2C
-
C_BASEADDR + 0x3C
Write⁽²⁾
N/A⁽³⁾
Notes:
1. The latched interruptible condition is cleared by writing a 1 to that bit location. Writing a 1 to a bit location that is 0
has no effect. Likewise, writing a 0 to a bit location that is 1 has no effect. Multiple bits may be cleared in a single
write.
2. Reset if written with 0xA5.
3. If read, these registers will return 0x0. Writing these registers will have no effect.
Interrupt Interface
The interrupt signals generated by the XPS LL FIFO are managed by the ISR and IER registers. An overview
diagram of the interrupt control structure is show in Figure 4.
Figure Top x-ref 4
XPS_LL_FIFO Interrupts
0123456789
0123456789
all zeros
...
...
ISR (0x0)
31
Read / Clear
on write of ‘1’
31
IER (0x4)
Read / Write
OR
Interrupt
Figure 4: Interrupt Control Structure
DS568_04_101708
DS568 March 1, 2011
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