DS568 Datasheet, PDF (15/22 Pages) Xilinx, Inc – LogiCORE IP XPS LL FIFO

LogiCORE IP XPS LL FIFO (v1.02a)
which corresponds to 13 to 16 bytes. The maximum packet that may be transmitted is limited by the size of the FIFO
and is 510 words (including partial final word) or 2037 to 2040 bytes.
Figure Top x-ref 9
0
31
Data Value
Figure 9: Transmit Data FIFO Data Write Port (offset 0x10)
Table 9: Transmit Data FIFO Data Write Port Bit Definitions
Bit(s)
Name
Core Access
Reset
Value
Description
0-31
Write Data Value
Write
N/A Transmit Data FIFO Write Value.
DS568_09_101708
Receive Data FIFO Reset Register (RDFR)
The Receive Data FIFO Reset Register, Figure 10, is actually not a register but, rather, a write-only address, which,
when written with a specific value, generates a reset for the Receive Data FIFO.
This reset will not occur until receive activity on the RX LocalLink has completed (for example, it only can occur
during inactive times on the RX LocalLink) and will only affect the receive circuitry in this core. This prevents the
core on the other end of the LocalLink from transmitting a partial packet which may cause failure condition in that
core.
Because of this mode of operation, it is possible that if the LocalLink is stuck in the middle of a LocalLink
transaction (i.e., if a packet is received over the LocalLink that exceeds the FIFO size of this core causing this core’s
destination ready to go inactive in the middle of a transfer), that the reset will never occur. In such cases it will be
necessary to use the LocalLink Reset.
Figure Top x-ref 10
0
24 25
31
0x0
0xA5
Figure 10: Receive Data FIFO Reset Register (offset 0x18)
Table 10: Receive Data FIFO Reset Register Bit Definitions
Bit(s)
Name
Core Access
Reset
Value
Description
0-31 Reset Key
Write
Reset Write Value.
N/A "0x000000A5" - Generate a reset.
Others - No effect.
DS568_10_101708
DS568 March 1, 2011
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Product Specification