DS568 Datasheet, PDF (22/22 Pages) Xilinx, Inc – LogiCORE IP XPS LL FIFO

LogiCORE IP XPS LL FIFO (v1.02a)
Revision History
Date
10/17/08
02/11/09
4/24/09
6/23/10
9/21/10
3/1/11
Version
1.0
1.1
1.6
1.7
1.8
1.9
Revision
Initial Xilinx release.
Incorporate CR#501446; Added Reserved Registers information
Replaced references to supported device families and tool name(s) with hyperlink to PDF file.
Incorporated CR480350 to update SOP and EOP terminology.
Updated for 12.3 release; made minor edits.
Updated for 13.1 release.
Notice of Disclaimer
Xilinx is providing this design, code, or information (collectively, the “Information”) to you “AS-IS” with no
warranty of any kind, express or implied. Xilinx makes no representation that the Information, or any particular
implementation thereof, is free from any claims of infringement. You are responsible for obtaining any rights you
may require for any implementation based on the Information. All specifications are subject to change without
notice. XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
ADEQUACY OF THE INFORMATION OR ANY IMPLEMENTATION BASED THEREON, INCLUDING BUT
NOT LIMITED TO ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
FROM CLAIMS OF INFRINGEMENT AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR
FITNESS FOR A PARTICULAR PURPOSE. Except as stated herein, none of the Information may be copied,
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including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior
written consent of Xilinx.
DS568 March 1, 2011
www.xilinx.com
22
Product Specification