DS568 Datasheet, PDF (4/22 Pages) Xilinx, Inc – LogiCORE IP XPS LL FIFO

LogiCORE IP XPS LL FIFO (v1.02a)
Table 1: I/O Signals (Cont’d)
Signal Name
Sl_SSize(0:1)
Sl_wait
Sl_rearbitrate
Sl_wrDAck
Sl_wrComp
Interface
PLB bus
PLB bus
PLB bus
PLB bus
Signal Type
O
O
O
O
PLB bus
O
Sl_wrBTerm
PLB bus
O
Sl_rdDBus(0:C_SPLB_DWIDTH-1)
Sl_rdWdAddr(0:3)
Sl_rdDAck
Sl_rdComp
PLB bus
O
PLB bus
O
PLB bus
O
PLB bus
O
Sl_rdBTerm
PLB bus
O
Sl_MBusy(0:C_SPLB_NUM_
MASTERS-1)
Sl_MWrErr(0:C_SPLB_NUM_ MASTERS-1)
Sl_MRdErr(0:C_SPLB_NUM_MASTERS-1)
Sl_MIRQ(0:C_SPLB_NUM_MASTERS-1)
LLink_rst
Tx_llink_din(31:0)
Tx_llink_src_rdy_n
Tx_llink_dest_rdy_n
PLB bus
O
PLB bus
O
PLB bus
O
PLB bus
O
LocalLink Signals
LLink
O
TX LocalLink Signals
LLink
O
LLink
O
LLink
I
Tx_llink_sof_n
Tx_llink_sop_n
Tx_llink_eof_n
Tx_llink_eop_n
Tx_llink_rem_n(3:0)
Rx_llink_din(31:0)
Rx_llink_src_rdy_n
Rx_llink_dest_rdy_n
LLink
O
LLink
O
LLink
O
LLink
O
LLink
O
RX LocalLink Signals
LLink
I
LLink
I
LLink
O
Rx_llink_sof_n
Rx_llink_sop_n
LLink
I
LLink
I
Init Status
Description
Slave data bus size
Slave wait indicator
Slave rearbitrate bus indicator
Slave write data acknowledge
Slave write transfer complete
indicator
Slave terminate write burst
transfer
Slave read data bus
Slave read word address
Slave read data acknowledge
Slave read transfer complete
indicator
Slave terminate read burst
transfer
Slave busy indicator
Slave error indicator
Slave error indicator
LocalLink Reset
TX LocalLink Data Bus
TX LocalLink Source Ready
TX LocalLink Destination
Ready
TX LocalLink Start of Frame
TX LocalLink Start of Payload
TX LocalLink End of Frame
TX LocalLink End of Payload
TX LocalLink Rem
RX LocalLink Data Bus
RX LocalLink Source Ready
RX LocalLink Destination
Ready
RX LocalLink Start of Frame
RX LocalLink Start of Payload
DS568 March 1, 2011
www.xilinx.com
4
Product Specification