DS568 Datasheet, PDF (16/22 Pages) Xilinx, Inc – LogiCORE IP XPS LL FIFO

LogiCORE IP XPS LL FIFO (v1.02a)
Receive Data FIFO Occupancy Register (RDFO)
The Receive Data FIFO Occupancy Register, Figure 11, is a read-only register that gives the occupancy status of the
Receive Data FIFO.
Figure Top x-ref 11
0
22 23
31
Reserved
Occupancy
Figure 11: Receive Data FIFO Occupancy Register (offset 0x1C)
DS568_11_101708
Table 11: Receive Data FIFO Occupancy Register Bit Definitions
Bit(s)
Name
Core
Access
Reset Value
Description
0-22
Reserved
Read
0x0
Reserved. These bits are reserved for future definition and
will always return all zeros.
23-31 Occupancy
Read
Receive Data FIFO Occupancy. This is the unsigned value
reflecting a current snapshot of the number of 32-bit wide locations
0x0
in use for data storage in the receive Data FIFO memory core. This
value is only updated after a packet is successfully received and
therefore can be used to determine (a non-zero value) if a receive
packet is ready to be processed.
Receive Data FIFO Data Read Port RDFD)
The Receive Data FIFO Data Read Port, Figure 12, is a 32-bit wide address location for reading data from the
Receive Data FIFO. The smallest packet that may be received is four 32-bit words (including partial final word)
which corresponds to 13 to 16 bytes. The maximum packet that may be received is limited by the size of the FIFO
and is 510 words (including partial final word) or 2037 to 2040 bytes.
Figure Top x-ref 12
0
22 23
31
Reserved
Data Value
Occupancy
Figure 12: Receive Data FIFO Data Read Port (offset 0x20)
Table 12: Receive Data FIFO Data Read Port Bit Definitions
Bit(s)
Name
Core Access
Reset
Value
Description
0-31 Read Data Value
Read
N/A Receive Data FIFO Read Value.
DS568_121_101708
Transmit Length Register (TLR)
The transmit length Register shown in Figure 13 is used to store packet length values (the number of bytes in the
packet) corresponding to valid packets ready for transmit. The data for the packet is stored in the transmit data
FIFO. The data is written to the XPS LL FIFO over the external processor bus interface either by Central DMA or by
direct memory mapped access. When presenting a transmit packet to the XPS LL FIFO, the packet data should first
be written to the transmit data FIFO then write the length of the packet into the TLR.
DS568 March 1, 2011
www.xilinx.com
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Product Specification