DS568 Datasheet, PDF (7/22 Pages) Xilinx, Inc – LogiCORE IP XPS LL FIFO

LogiCORE IP XPS LL FIFO (v1.02a)
Table 3: Parameter Port Dependencies
Generic
or Port
Name
G4
C_SPLB_MID_WIDTH
P1
PLB_BE(0:(C_SPLB_
DWIDTH/8)-1)
P2
PLB_ABus(0:C_SPLB_WI
DTH-1)
P3
PLB_wrDBus(0:C_
SPLB_DWIDTH-1)
P4
M_BE(0:(C_SPLB_
AWIDTH/8)-1)
P5
M_ABus(0:C_SPLB_
AWIDTH-1)
P6
M_wrDBus(0:C_SPLB_
DWIDTH-1)
P7
PLB_RdDBus(0:C_
SPLB_DWIDTH-1)
P8
Sl_RdDBus(0:C_SPLB_
DWIDTH-1)
P9
Sl_MBusy(0:C_SPLB_
NUM_MASTERS-1)
P10
Sl_MErr(0:C_SPLB_
NUM_MASTERS-1)
P11
PLB_masterID(0:C_
SPLB_MID_WIDTH-1)
Affects
P11
Depends
Relationship Description
Specifies the Master ID bus width
G1
Width varies with the size of the Data bus.
G2
Width varies with the size of the Address bus.
G1
Width varies with the size of the Data bus.
G1
Width varies with the size of the Data bus.
G2
Width varies with the size of the Address bus.
G1
Width varies with the size of the Data bus.
G1
Width varies with the size of the Data bus.
G1
Width varies with the size of the Data bus.
G3
Width varies with the number of masters on the
PLB bus
G3
Width varies with the number of masters on the
PLB bus
G4
Width varies with the number of masters on the
PLB bus
DS568 March 1, 2011
www.xilinx.com
7
Product Specification