DS568 Datasheet, PDF (2/22 Pages) Xilinx, Inc – LogiCORE IP XPS LL FIFO

LogiCORE IP XPS LL FIFO (v1.02a)
Functional Description
The Xilinx XPS LL FIFO may be configured for specific systems by selecting the appropriate features through
parameter values, thereby providing a design with the minimum necessary resources while providing the desired
operational functions. Parameterizable features of the design are discussed in Design Parameters.
Overview
Figure 1 shows the major components in the XPS LL FIFO. The core consists of two FIFOs: a TX FIFO and an RX
FIFO. The TX uses one FIFO for the transmit data and for the length data. The RX uses one FIFO for the receive data
and the length data. In addition to the FIFOs, there is a register block, a PLBv46 interface, and a LocalLink interface.
Figure Top x-ref 1
XPS_LL_FIFO
PLB Attachment
Registers
Slave
32 Bit
Rx LocalLink
Interface
32 Bit
Tx LocalLink
Interface
Receive
Control
Transmit
Control
Interrupt
Controller
Receive
FIFO
(2 Kb)
Transmit
FIFO
(2 Kb)
PLBV46 Bus
FPGA Fabric
Figure 1: XPS LL FIFO Block Diagram
DS568_01_101708
I/O Signals
The XPS LL FIFO core uses a transparent bus EDK format to simplify generation of embedded systems by
simplifying the connection of signals between the XPS LL FIFO’s LocalLink interface and other IP LocalLink
interfaces such as the XPS LL TEMAC core. This is the same technique that allows the EDK tools to automatically
connect the PLBv46 signals.
The ports on the XPS LL FIFO which connect to the LocalLink are grouped into a virtual bus called LLink. For
example, the corresponding signals on the XPS LL TEMAC are grouped into virtual buses called LLink0 andLLink1
depending on what half is used.
To connect a XPS LL FIFO to an XPS LL TEMAC, the user designates to which half of the XPS LL TEMAC they wish
to connect by assigning the name to the virtual bus of the XPS LL FIFO that matches the name assigned to the half
of the XPS LL TEMAC to be used. In the signal list shown in Table 1, the signals that are assigned to the virtual bus
are designated with an interface value of LLink.
DS568 March 1, 2011
www.xilinx.com
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Product Specification