DS568 Datasheet, PDF (5/22 Pages) Xilinx, Inc – LogiCORE IP XPS LL FIFO

LogiCORE IP XPS LL FIFO (v1.02a)
Table 1: I/O Signals (Cont’d)
Signal Name
Rx_llink_eof_n
Rx_llink_eop_n
Rx_llink_rem_n(3:0)
Interface
LLink
LLink
LLink
Signal Type
I
I
I
Init Status
Description
RX LocalLink End of Frame
RX LocalLink End of Payload
RX LocalLink Rem
Design Parameters
To allow the user to generate a XPS LL FIFO that is tailored for their system, certain features are parameterizable.
This allows the user to have a design that only utilizes the resources required by their system and runs at the best
possible performance. The features that are parameterizable in the Xilinx XPS LL FIFO design are shown in Table 2.
Table 2: Design Parameters
Feature/Description
Parameter Name
Allowable Values
Default
Values
VHDL
Type
Top Level
Device family
C_FAMILY
virtex6, virtex5, virtex4, qvirtex4,
qrvirtex4, spartan3e, aspartan3e,
spartan3a, aspartan3a,
spartan3an, spartan3adsp,
aspartan3adsp, spartan6
virtex5
string
Device base address
C_BASEADDR
See note 1.
FFFFFFFF
std logic
vector
Device maximum address C_HIGHADDR
See note 1.
0x0
std logic
vector
PLBv46 Interface
PLB number of masters
C_SPLB1_NUM_MASTERS The number of Master Devices
connected to the PLB bus
1
integer
PLB master ID width
C_SPLB_MID_WIDTH
The width of the Master ID bus.
This is set to roundup(log2
(C_SPLB_NUM_MASTERS) See
3
note 2.
integer
PLB Smallest Master Width C_SPLB_SMALLES_MASTER Width of the smallest master that
will be interacting with this slave.
128
See note 2.
integer
PLB master device width C_SPLB_NATIVE_DWIDTH 32
32
Integer
non-VHDL
PLB address bus width (in C_SPLB_AWIDTH
32
bits)
32
integer
PLB data bus width (in bits) C_SPLB_DWIDTH
32,64,128
32
integer
Selects point-to-point or
shared PLB topology
C_SPLB_P2P
0 = Shared Bus Topology
1 = Point-to-Point Bus Topology
0
integer
Notes:
1. The default value will insure that the actual value is set, i.e., if the value is not set, a compiler error will be generated. The address
range must be at least 0x4000 (for example, 0x10000000 and 0x10003FFF). C_BASEADDR must be a multiple of the range,
where the range is C_HIGHADDR - C_BASEADDR +1.
2. The value of these parameters are automatically calculated by the XPS tools based on the system specified in the MHS file. The
value calculated by XPS for these parameters will override any values supplied in the system MHS file.
DS568 March 1, 2011
www.xilinx.com
5
Product Specification