DS568 Datasheet, PDF (17/22 Pages) Xilinx, Inc – LogiCORE IP XPS LL FIFO

LogiCORE IP XPS LL FIFO (v1.02a)
Once the packet length is written to the TLR it is automatically moved to the transmit data FIFO with the packet
data freeing up the TLR for another value. The packet length must be written to the TLR after the packet data is
written to the transmit data FIFO. It is not valid to write data for multiple packets to the transmit data FIFO before
writing the packet length values.
The action of writing to the transmit length register is used by the XPS LL FIFO to initiate the processing of transmit
packets across the LocalLink interface. This continues until all of the TLR values stored are processed. The transmit
packet size has to be more than 8 bytes in length.
The width of the TLR is wide enough to support packets up to 2048 bytes in length. The smallest packet that may
be transmitted is four 32-bit words (including partial final word) which corresponds to 13 to 16 bytes. The
maximum packet that may be transmitted is limited by the size of the FIFO and is 510 words (including partial final
word) or 2037 to 2040 bytes.
Figure Top x-ref 13
20 21
31
Reserved
Figure 13: Transmit Length Register (offset 0x14)
TXL
DS568_13_101708
Table 13: Transmit Length Register Bit Definitions
Bit(s)
Name
Core Access
Reset
Value
Description
0-20 Reserved
N/A
0x0
Reserved. These bits are reserved for future definition and will
always return all zeros.
21-31
TXL
Write
0x0
Transmit Length. The number of bytes of the corresponding transmit
packet stored in the transmit data FIFO.
Receive Length Register (RLR)
The receive length register shown in Figure 14is used to retrieve packet length values (the number of bytes in the
packet) corresponding to valid packets received. The data for the packet is stored in the receive data FIFO.
The length is written by the XPS LL FIFO when the packet is received across the RX LocalLink interface and the
receive data FIFO had enough locations that all of the packet data has been saved.
The RLR should only be read when a receive packet is available for processing (the receive occupancy is not zero).
Once the RLR is read, the receive packet data should be read from the receive data FIFO before the RLR is read
again.
The RLR values are stored in the receive data FIFO by the XPS LL FIFO with each packet’s data. The RLR value for
the next packet to be processed is moved to the RLR when the previous RLR value has been read.
This register is wide enough to support packets up to 2048 bytes in length. The smallest packet that may be received
is four 32-bit words (including partial final word) which corresponds to 13 to 16 bytes. The maximum packet that
DS568 March 1, 2011
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Product Specification