DS568 Datasheet, PDF (8/22 Pages) Xilinx, Inc – LogiCORE IP XPS LL FIFO

LogiCORE IP XPS LL FIFO (v1.02a)
Figure 2 shows the XPS LL FIFO connected to the XPS LL TEMAC.
Figure Top x-ref 2
XPS LL TEMAC
PHY1 mgmnt interface
Registers
PHY0 mgmnt interface
FPGA Fabric
PHY1 datainterface
LLink1
XPS LL FIFO
LLink
PHY0 data interface
LLink0
XPS LL FIFO
LLink
PLBV46 Bus
Notes:
1. The use of two XPS LL FIFO cores is optional. When using only one half of
Figure 2: System with XPS LL FIFO connected to dual XPS LL TEMAC⁾
Figure 3 shows a partial code segment from an EDK MHS file which shows an example connection between two
XPS LL FIFO cores and a XPS LL TEMAC core.
DS568 March 1, 2011
www.xilinx.com
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Product Specification