DS568 Datasheet, PDF (14/22 Pages) Xilinx, Inc – LogiCORE IP XPS LL FIFO

LogiCORE IP XPS LL FIFO (v1.02a)
Because of this mode of operation, it is possible that if the LocalLink becomes stuck in the middle of a LocalLink
transaction, for instance, waiting for the destination ready to go active in the middle of a transfer, that the reset will
never occur. In such cases it will be necessary to use the LocalLink Reset.
Figure Top x-ref 7
0
24 25
31
0x0
Figure 7: Transmit Data FIFO Reset Register (offset 0x8)
Table 7: Transmit Data FIFO Reset Register Bit Definitions
Bit(s)
Name
Core Access
Reset
Value
Description
0-31 Reset Key
Write
Reset Write Value.
N/A "0x000000A5" - Generate a reset.
others - No effect.
0xA5
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Transmit Data FIFO Vacancy Register (TDFV)
The Transmit Data FIFO Vacancy Register, Figure 8, is a read-only register that gives the vacancy status of the
Transmit Data FIFO.
Figure Top x-ref 8
0
22 23
31
Reserved
Vacancy
Figure 8: Transmit Data FIFO Vacancy Register (offset 0xC)
DS568_08_101708
Table 8: Transmit Data FIFO Vacancy Register Bit Definitions
Bit(s)
Name
Core
Access
Reset Value
Description
0-22 Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will
always return all zeros.
23-31 Vacancy
Read
0x01FE
Transmit Data FIFO Vacancy. This is the unsigned value
reflecting a current snapshot of the number of 32-bit wide locations
available for data storage in the transmit Data FIFO memory core.
Notes:
1. One location is reserved for the storage of the transmit length value for the first packet.
Transmit Data FIFO Data Write Port (TDFD)
The Transmit Data FIFO Data Write Port, Figure 9, is a 32-bit wide address location for writing data into the
Transmit Data FIFO. The smallest packet that may be transmitted is four 32-bit words (including partial final word)
DS568 March 1, 2011
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Product Specification