DS568 Datasheet, PDF (6/22 Pages) Xilinx, Inc – LogiCORE IP XPS LL FIFO

LogiCORE IP XPS LL FIFO (v1.02a)
Detailed Parameter Descriptions
C_FAMILY
The family parameter is required to implement the core using family specific architecture features. This parameter
is automatically updated by the EDK tools based on the project target device information.
C_BASEADDR and C_HIGHADDR
These values are used to generate the read and write enables for the FIFOs and registers and are byte addresses. The
address range defined by these parameters must be at least 0x4000. For example, if the C_BASEADDR is set to
0x10000000, then C_HIGHADDR must be set to at least 0x10003FFF. These parameters must be initialized because
the default values have been selected so that they will generate an error during build if left unchanged.
C_SPLB_NUM_MASTERS
This parameter is automatically updated by the EDK tools based on the project information.
C_SPLB_MID_WIDTH
This parameter is automatically updated by the EDK tools based on the project information.
C_SPLB_SMALLEST_MASTER
This parameter is defined as an integer and is equal to the native data width of the smallest Master connected to the
PLB bus that will be accessing the plbv46_slave attachment. This generic is used to generate and optimize steering
logic in the slave attachment. This parameter is automatically updated by the EDK tools based on the project
information.
C_SPLB_AWIDTH and C_SPLB_DWIDTH
These parameters should always be set to 32 and 32, 64, and 128 respectively. They are updated by the EDK Tools
automatically based on the project information.
C_SPLB_P2P
This parameter is defined as an integer. Setting this parameter to 0 will configure the PLB slave for a PLB shared bus
application. Setting this parameter to 1 will configure the PLB slave for a PLB point-to-point bus application. In a
point-to-point configuration the core acknowledges all address cycles on the PLB. This reduces some FPGA
resources. Latency is also reduced in a point-to-point configuration.
Parameter - Port Dependencies
The width of some of the XPS LL FIFO signals depend on parameters selected in the design. The dependencies
between the XPS LL FIFO design parameters and I/O signals are shown in Table 3.
Table 3: Parameter Port Dependencies
Generic
or Port
Name
Affects
Depends
Relationship Description
Design Parameters
G1
C_SPLB_DWIDTH
P1, P3, P4, P6,
P7, P8
Specifies the Data Bus width
G2
C_SPLB_AWIDTH
P2, P5
Specifies the Address Bus width
G3
C_SPLB_NUM_MASTERS
P9, P10
Specifies the number of masters on the PLB bus
DS568 March 1, 2011
www.xilinx.com
6
Product Specification