DS568 Datasheet, PDF (3/22 Pages) Xilinx, Inc – LogiCORE IP XPS LL FIFO

Table 1: I/O Signals
Signal Name
SPLB_CLK
SPLB_RST
IP2INTC_Irpt
PLB_ABus(0:31)
PLB_UABus(0:31)
PLB_PAValid
PLB_SAValid
PLB_rdPrim
PLB_wrPrim
PLB_masterID(0:C_SPLB_MID_
WIDTH -1)
PLB_abort
PLB_buslock
PLB_RNW
PLB_BE(0:(C_SPLB_DWIDTH/8)-1)
PLB_MSize(0:1)
PLB_size(0:3)
PLB_type(0:2)
PLB_lockErr
PLB_wrDBus(0:C_sPLB_
DWIDTH-1)
PLB_wrBurst
PLB_rdBurst
PLB_wrpendReq
PLB_rdpendReq
PLB_wrpendPri(0:1)
PLB_rdpendPri(0:1)
PLB_reqPri(0:1)
PLB_TAttribute(0:15)
Sl_addrAck
LogiCORE IP XPS LL FIFO (v1.02a)
Interface Signal Type Init Status
Description
Top Level System Signals
System
I
System clock
System
I
System Reset (active high)
System
O
System Interrupt
PLBv46 Signals
PLB bus
I
PLB address bus
PLB bus
I
PLB upper address bus
PLB bus
I
PLB primary address valid
indicator
PLB bus
I
PLB secondary address valid
indicator
PLB bus
I
PLB secondary to primary read
request indicator
PLB bus
I
PLB secondary to primary write
request indicator
PLB bus
I
PLB current master indentifier
PLB bus
I
PLB bus
I
PLB bus
I
PLB bus
I
PLB bus
I
PLB bus
I
PLB bus
I
PLB bus
I
PLB bus
I
PLB abort bus request indicator
PLB bus lock
PLB Read not Write
PLB byte enables
PLB master data bus size
PLB transfer size
PLB transfer type
PLB lock error indicator
PLB write data bus
PLB bus
I
PLB bus
I
PLB bus
I
PLB bus
I
PLB bus
I
PLB bus
I
PLB bus
I
PLB bus
i
PLB bus
O
PLB burst write transfer
indicator
PLB burst read transfer
indicator
PLB pending bus request
indicator
PLB pending bus request
indicator
PLB pending request priority
PLB pending request priority
PLB current request priority
PLB Attribute
Slave address acknowledge
DS568 March 1, 2011
www.xilinx.com
3
Product Specification