DS568 Datasheet, PDF (11/22 Pages) Xilinx, Inc – LogiCORE IP XPS LL FIFO

LogiCORE IP XPS LL FIFO (v1.02a)
Interrupt Status Register (ISR)
The Interrupt Status Register is shown in Figure 5. This register combined with the IER register define the interrupt
interface of the XPS LL FIFO. The Interrupt Status register uses one bit to represent each XPS LL FIFO internal
interruptible condition.
Once an interruptible condition occurs, it will be captured in this register (represented as the corresponding bit
being set to 1) even if the condition goes away. The latched interruptible condition is cleared by writing a 1 to that
bit location. Writing a 1 to a bit location that is 0 has no effect. Likewise, writing a 0 to a b0it location that is 1 has no
effect. Multiple bits may be cleared in a single write.
For any bit set in the Interrupt Status Register, a corresponding bit must be set in the Interrupt Enable Register for
the IP2INTC_Irpt signal to be driven active high out of the XPS LL FIFO.
The bits are detailed in Table 5.Interrupt Enable Register (IER)
Figure Top x-ref 5
RPUE
RPURE
TC
TSE RRC
0123456789
31
RPORE
RC
TPOE
TRC
Reserved
DS568_05_101708
Figure 5: Interrupt Status Register (offset 0x0)
Table 5: Interrupt Status Register Bit Definitions
Bit(s)
Name
Core Access
Reset
Value
Description
Receive Packet Underrun Read Error: This interrupt occurs when an
attempt is made to read the receive length register when it is empty. The
0
RPURE
Read/Clear on
Write of "1"
0
data read is not valid. A reset of the receive logic is required to recover.
"0" = No interrupt pending.
"1" = Interrupt pending.
Receive Packet Overrun Read Error. This interrupt occurs when more
words are read from the receive data FIFO than are in the packet being
processed. Even though the FIFO may not be empty, the read has gone
1
RPORE
Read/Clear on
Write of "1"
0
beyond the current packet and removed data from the next packet. A reset
of the receive logic is required to recover.
"0" = No interrupt pending.
"1" = Interrupt pending.
Receive Packet Underrun Error. This interrupt occurs when an attempt is
made to read the receive FIFO when it is empty. The data read is not valid.
2
RPUE
Read/Clear on
Write of "1"
0
A reset of the receive logic is required to recover.
"0" = No interrupt pending.
"1" = Interrupt pending.
Transmit Packet Overrun Error. This interrupt is generated if an attempt is
made to write to the transmit data FIFO when it is full. A reset of the transmit
3
TPOE
Read/Clear on
Write of "1"
0
logic is required to recover.
"0" = No interrupt pending.
"1" = Interrupt pending.
DS568 March 1, 2011
www.xilinx.com
11
Product Specification