DS568 Datasheet, PDF (13/22 Pages) Xilinx, Inc – LogiCORE IP XPS LL FIFO

LogiCORE IP XPS LL FIFO (v1.02a)
Table 6: Interrupt Enable Register Bit Definitions
Bit(s)
Name
Core Access
Reset
Value
Description
0
RPUREE Read/Write
Receive Packet Underrun Read Error Enable. This bit is the interrupt
enable for the RPURE bit in the ISR.
0
"0" = Mask Interrupt.
"1" = Enable Interrupt.
1
RPOREE Read/Write
Receive Packet Overrun Read Error Enable. This bit is the interrupt
enable for the RPORE bit in the ISR.
0
“0” = Mask Interrupt.
"1" = Enable Interrupt.
2
RUREE Read/Write
Receive Packet Underrun Error Enable. This bit is the interrupt enable for
the RURE bit in the ISR.
0
"0" = Mask Interrupt.
"1" = Enable Interrupt.
Transmit Packet Overrun Error Enable. This bit is the interrupt enable for
the TORE bit in the ISR.
3
TOREE Read/Write
0
"0" = Mask Interrupt.
"1" = Enable Interrupt.
Transmit Complete Enable. This bit is the interrupt enable for the TC bit in
the ISR.
4
TCE
Read/Write
0
"0" = Mask Interrupt.
"1" = Enable Interrupt.
Receive Complete Enable. This bit is the interrupt enable for the RC bit in
the ISR.
5
RCE
Read/Write
0
"0" = Mask Interrupt.
"1" = Enable Interrupt.
6
TMSEE Read/Write
Transmit Size Error Enable. This bit is the interrupt enable for the TMSE
bit in the ISR.
0
"0" = Mask Interrupt.
"1" = Enable Interrupt.
Transmit Reset Complete Enable. This bit is the interrupt enable for the
TRC bit in the ISR.
7
TRCE
Read/Write
1
"0" = Mask Interrupt.
"1" = Enable Interrupt.
Receive Reset Complete Enable. This bit is the interrupt enable for the
RRC bit in the ISR.
8
RRCE
Read/Write
1
"0" = Mask Interrupt.
"1" = Enable Interrupt.
9-31 Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will
always return all zeros.
Transmit Data FIFO Reset Register (TDFR)
The Transmit Data FIFO Reset Register, Figure 7, is not an actual register. It is a write-only address, which when
written with a specific value, generates a reset for the Transmit Data FIFO. This reset will not occur until transmit
activity on the TX LocalLink has completed. The reset can occur only during inactive times on the TX LocalLink and
will affect only the transmit circuitry in this core, thereby preventing the core on the other end of the LocalLink from
receiving a partial packet which may cause a failure condition in that core.
DS568 March 1, 2011
www.xilinx.com
13
Product Specification