DS568 Datasheet, PDF (18/22 Pages) Xilinx, Inc – LogiCORE IP XPS LL FIFO

LogiCORE IP XPS LL FIFO (v1.02a)
may be received is limited by the size of the FIFO and is 510 words (including partial final word) or 2037 to 2040
bytes.
Figure Top x-ref 14
0
20 21
3
Reserved
RXL
Figure 14: Receive Length Register (offset 0x24)
DS568_14_10
Table 14: Receive Length Register Bit Definitions
Bit(s)
Name
Core Access
Reset
Value
Description
0-20 Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will
always return all zeros.
21-31
RXL
Read
0x0
Receive Length. The number of bytes of the corresponding receive
data stored in the receive data FIFO.
LocalLink Reset Register (LLR)
The LocalLink Register, Figure 15, is not an register. It is a write-only address, which when written with a specific
value, generates an immediate reset for the entire core as well as driving a reset on the external output Llink_rst
which can be used to reset the core on the other end of the LocalLink.
Figure Top x-ref 15
0
24 25
31
0x0
Figure 15: LocalLink Reset Register (offset 0x28)
Table 15: LocalLink Reset Register Bit Definitions
Bit(s)
Name
Core Access
Reset
Value
Description
0-31 Reset Key
Write
Reset Write Value.
N/A "0x000000A5" - Generate a reset.
Others - No effect.
0xA5
DS568_15_101708
Reserved Registers
Reading from reserved registers will return zeros, and writing to reserved registers will not have any effect.
However, any accesses to address offset 0x40 and above will cause undefined results.
DS568 March 1, 2011
www.xilinx.com
18
Product Specification