DS568 Datasheet, PDF (19/22 Pages) Xilinx, Inc – LogiCORE IP XPS LL FIFO

LogiCORE IP XPS LL FIFO (v1.02a)
Basic Usage
The XPS LL FIFO was designed to provide processor bus access to a LocalLink interface to be used with other IP
such as the XPS LL TEMAC. Systems must be built through the Embedded Development Kit to attach the XPS LL
FIFO, XPS LL TEMAC, processor, memory, busses, clocking and addition embedded components.
The section is not intended to describe the building of systems, EDK documents describe this process. This section
briefly describes operation of the XPS LL FIFO through register accesses using the XPS LL TEMAC as an example.
Packets will automatically be transmitted by writing packet data to the transmit data FIFO followed by writing a
length in the TLR.
Receiving packets works in a fashion similar to transmission, although the steps are reversed. Polling of the ISR
receive complete or the receive data FIFO occupancy register (not zero) indicates reception of a packet. Reading the
RLR provides the packet length in bytes. Given the number of received packet bytes, the appropriate number of
reads of the Read data FIFO will provide the packet data.
Table 16 illustrates a power-up read of the registers followed by a transmission and reception of a single packet.
Refer to the register definitions for further information and options.
Table 16: XPS LL FIFO Sample TX/RX Usage
Register
Access
Value
Activity
Power-up read of register values
ISR
Read Word
0x01800000
Read interrupt status register
ISR
Write Word
0xFFFFFFFF
Write to clear reset done interrupt bits
ISR
Read Word
0x00000000
Read interrupt status register
IER
Read Word
0x00000000
Read interrupt enable register
TDFV
Read Word
0x000001FE
Read the transmit FIFO vacancy
RDFO
Read Word
0x00000000
Read the receive FIFO occupancy
Transmit a Packet
TXFIFO_DATA Write Word
0xFFFFFFFF
4 bytes of destination address
TXFIFO_DATA Write Word
0xFFFF9ABC
2 bytes of destination address (0xFFFF) 2 bytes source address
(0x9ABC)
TXFIFO_DATA Write Word
0x12345678
4 bytes of source address
TXFIFO_DATA Write Word
0x002E0001
2 bytes length (0x002E) 2 bytes packet data (0x0001)
TXFIFO_DATA Write Word
0x00010203
4 bytes of packet data
TXFIFO_DATA Write Word
0x04050607
4 bytes of packet data
TXFIFO_DATA Write Word
0x08090A0B
4 bytes of packet data
TXFIFO_DATA Write Word
0x0C0D0E0F
4 bytes of packet data
TXFIFO_DATA Write Word
0x10111213
4 bytes of packet data
TXFIFO_DATA Write Word
0x14151617
4 bytes of packet data
TXFIFO_DATA Write Word
0x18191A1B
4 bytes of packet data
TXFIFO_DATA Write Word
0x0C0D0E0F
4 bytes of packet data
TXFIFO_DATA Write Word
0x20212223
4 bytes of packet data
TXFIFO_DATA Write Word
0x24252627
4 bytes of packet data
TXFIFO_DATA Write Word
0x28292A2B
4 bytes of packet data
TDFV
Read Word
0x000001EF
Read the transmit FIFO vacancy
TLR
Write Word
0x0000003C
Transmit length (0x3C = 60 bytes), this starts transmission
ISR
Read Word
0x08000000
A typical value after Tx Complete is indicated by interrupt
ISR
Write Word
0xFFFFFFFF
Write to clear reset done interrupt bits
DS568 March 1, 2011
www.xilinx.com
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Product Specification