DS565 Datasheet, PDF (9/28 Pages) Xilinx, Inc – PLBV46 Master Burst

PLBV46 Master Burst (v1.01a)
Allowable Parameter Combinations
The current implementation of the PLBV46 Master Burst has the following restrictions that apply to parameter
value settings:
• The assigned value for C_MPLB_AWIDTH is currently restricted to 32.
• The value of C_MPLB_DWIDTH must be greater than or equal to the value assigned to
C_MPLB_NATIVE_DWIDTH.
Parameter - Port Dependencies
Table 3: PLBV46 Master Burst Parameter-Port Dependencies
Name
(Generic or Port)
Affects
(Port)
Depends
(Generic)
Design Parameters
C_MPLB_AWIDTH
IP2Bus_Mst_Addr
C_MPLB_DWIDTH
M_BE
C_MPLB_DWIDTH
M_wrDBus
C_MPLB_DWIDTH
PLB_MRdDBus
C_MPLB_NATIVE_DWIDTH IP2Bus_Mst_BE
C_MPLB_NATIVE_DWIDTH Bus2IP_MstRd_d
C_MPLB_NATIVE_DWIDTH IP2Bus_MstWr_d
C_MPLB_NATIVE_DWIDTH Bus2IP_MstRd_REM
C_MPLB_NATIVE_DWIDTH IP2Bus_MstWr_REM
Relationship Description
The Parameter directly sets the ports
width.
The BE Bus width is derived from the
parameter value by dividing it by 8.
The port width is directly set by the
parameter value.
The port width is directly set by the
parameter value.
The IPIC BE Bus width is derived from
the parameter value by dividing it by 8.
The IPIC Read LocalLink Data port width
is directly set by the parameter value.
The IPIC LocalLink Write Data port width
is directly set by the parameter value.
The IPIC Read LocalLink REM port width
is derived from the parameter value by
dividing it by 8.
The IPIC Write LocalLink REM port width
is derived from the parameter value by
dividing it by 8.
DS565 December 14, 2010
www.xilinx.com
9
Product Specification