DS565 Datasheet, PDF (8/28 Pages) Xilinx, Inc – PLBV46 Master Burst

PLBV46 Master Burst (v1.01a)
Design Parameters
The PLBV46 Master Burst provides for User interface tailoring via VHDL Generic parameters. These parameters are
detailed in the following table. The FPGA Family Type parameter is used to select the target FPGA family type.
Currently, this design supports Virtex-4, Virtex-5, and Spartan-3 family of devices.
Table 2: PLBV46 Master Burst Design Parameters
Feature/Description
Parameter Name
Allowable Values
PLB I/O Specification
Specifies the Number of Used
C_MPLB_AWIDTH
32
Address bits out of the available 64
bits of PLBV46 addressing
Width of the PLB Data Bus to
which the Master is attached
C_MPLB_DWIDTH
32, 64, 128
Specifies the internal native data C_MPLB_NATIVE_DWIDTH
width of the Master
32, 64, 128
Narrow Slave Support
Indicates the smallest Native Data
Width of any Slave attached to the
PLBV46 Bus used by the Master
(1)
C_MPLB_SMALLEST_SLAVE
32, 64, 128
Default
Values
VHDL
Type
32
integer
32
integer
32
integer
32
integer
This parameter is used to override
the automatic inclusion of the
Conversion Cycle and Burst length
Expansion logic ⁽¹⁾
C_INHIBIT_CC_BLE_INCLUSION
0, 1
0 = Allow automatic
inclusion of CC and
BLE logic
1 = Inhibit automatic
inclusion of the CC and
BLE logic
FPGA Family Type
Xilinx FPGA Family
C_FAMILY
virtex4,virtex5,
spartan3a, aspartan3a,
spartan3, aspartan3,
spartan3e, aspartan3e,
spartan3adsp,
aspartan3adsp
0
virtex5
integer
string
Note: If the Master is parameterized to have 64 or 128 bit Native Data Width and it potentially can access a Slave that is
narrower than the requested data transfer size by the Master (indicated by the C_MPLB_SMALLEST_SLAVE parameter value),
then Conversion Cycle and Burst Length Expansion logic is required by the Master to complete the transfer. Masters that are
parameterized to 32-bit Native Data Width do not need the logic regardless of target Slave data width.
DS565 December 14, 2010
www.xilinx.com
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Product Specification