DS565 Datasheet, PDF (18/28 Pages) Xilinx, Inc – PLBV46 Master Burst

PLBV46 Master Burst (v1.01a)
Write Address Phase Timeout
An attempted single data beat write operation that results in an Address Phase timeout is shown in Figure 10. The
Master has a Native Data Width of 32 bits and the PLB data width is 32 bits. The Master’s MD_Error output is
asserted and held upon detection of the PLB_MTimeout assertion. The Master’s request, address, and qualifiers are
removed from the PLB on the following PLB clock after the timeout indication and a timeout status is relayed to the
User logic on the IPIC. The associated LocalLink interface (if it is still active) will be forced to Discontinue by the
Master. For this example, the assertion of MD_Error is cleared by the MPLB_Rst input from the PLBV46 interface.
X-Ref Target - Figure 10
0ns
MPLB_Clk
MPLB_Rst
100ns
MD_Error
M_request
M_buslock
M_priority
0
M_ABus
M_RNW
M_BE
M_MSize
1
M_size
M_type
0
M_wrDBus
PLB_MTimeout
PLB_MaddrAck
PLB_MSsize
PLB_MRearbitrate
PLB_MBusy
PLB_MRdDbus
PLB_MRdDAck
PLB_MWrDAck
PLB_MWrErr
PLB_MRdErr
IP2Bus_MstRd_Req
IP2Bus_MstWr_Req
IP2Bus_Mst_Type
IP2Bus_Mst_Addr
IP2Bus_Mst_BE
IP2Bus_Mst_Length
IP2Bus_Mst_Lock
IP2Bus_Mst_Reset
Bus2IP_Mst_CmdAck
Bus2IP_Mst_Cmplt
Bus2IP_Mst_Error
Bus2IP_Mst_Rearbitrate
Bus2IP_Mst_Cmd_Timeout
IP2Bus_MstWr_d[0:31]
IP2Bus_MstWr_rem[0:3]
IP2Bus_MstWr_sof_n
IP2Bus_MstWr_eof_n
IP2Bus_MstWr_src_rdy_n
IP2Bus_MstWr_src_dsc_n
Bus2IP_MstWr_dst_rdy_n
Bus2IP_MstWr_dst_dsc_n
WD0
"0000"
200ns
500ns
600n 900
0
10000004
FF
0
1
0
0
0
WD0
10000004
F
XXX
Figure 10: Single Data Beat Write Resulting in PLB Address Phase Timeout
DS565 December 14, 2010
www.xilinx.com
18
Product Specification