DS565 Datasheet, PDF (25/28 Pages) Xilinx, Inc – PLBV46 Master Burst

PLBV46 Master Burst (v1.01a)
Transfer Throttling
The main rule that must be followed is the limitation that once a LocalLink transfer is started, the IP Client is not
allowed to throttle the LocalLink transfer by de-asserting the applicable ready signal or asserting the discontinue
signal. The reason this is required is that without the FIFO’s, the PLB Master will directly couple PLB Data phase
protocol to the LocalLink transfer protocol with only minor translation. One of the rules of PLB is that a PLB Master
is not allowed to throttle a data phase operation once it starts. Thus, since the PLB and LocalLink are almost directly
coupled, the "no throttling" rule gets pushed to the LocalLink transfer and to the IP Client.
Conversely, the PLB Slave device is allowed to throttle the PLB Data phase at any time. With the PLB and the
LocalLink directly coupled during the data phase, a LocalLink transfer may be throttled at any time by the Master
side as a result of PLB Slave throttling. This is generally not a hard environment for the IP Client on the Read
LocalLink interface. However, in the write LocalLink direction, the IP Client logic must be able to provide the next
sequential data beat of data to transfer when a PLB Slave has throttled the write transfer and then stops throttling.
This may require design forethought especially if the IP Client is sourcing data from a memory element that has a
read latency (such as BRAM) or a FIFO that is reading ahead and has to recover at the throttle condition.
Transfer Termination
All LocalLink transfers must terminate with the assertion of the eof_n delimiter and the simultaneous assertion of
the src_rdy_n and the dst_rdy_n signals. In the case of the Read LocalLink interface, the Master will assert the last
read data value from the PLB on the Bus2IP_MstRd_d(0:n), and assert Bus2IP_MstRd_src_rdy_n and the
Bus2IP_MstRd_eof_n. This state will continue until the IP asserts the IP2Bus_MstRd_dst_rdy_n (this should
already be asserted). In the case of the Write LocalLink, the User logic must assert the last write data value for the
PLB on the IP2Bus_MstWr_d(0:n), and assert IP2Bus_MstWr_src_rdy_n and the IP2Bus_MstWr_eof_n. The Master
will assert the Bus2IP_MstWr_dst_rdy_n when the data beat has been consumed by the PLB. Note that for a single
data beat transfer, the LocalLink transfer will only be one data beat with the simultaneous assertion of the sof_n in
conjunction with the other termination signaling.
When the Master recognizes that the LocalLink transfer has completed, the BUS2IP_Mst_CmdCmplt will be
asserted for one PLB clock cycle, indicating the Master has finished all processing for the command and is ready for
the next command.
PLB Rearbitration
The User Logic should ignore the Bus2IP_Mst_Rearbitrate status reply. This signal has no operational ramifications
for the User logic.
Conversion Cycle Operations
Conversion Cycles are required if the Master attempts to read or write data from/to a PLB Slave if the following
conditions apply:
• The Master is requesting a Single Data Beat transfer.
• The Slave has a Native Data Width that is narrower than the Master’s Native Data Width. The Slave will report
it’s Native Data Width to the Master via the Sl_Ssize(0:1) output signals during the PLB clock period that
includes the assertion of the Sl_AddrAck signal. This is independent of the PLB data width.
• The Master’s assertion of the M_BE(0:n) signals indicates an attempt to transfer more data bytes than the Slave
can read or write in a single data beat or the alignment of the asserted BE cross the Native Data Width
boundary of the target Slave.
DS565 December 14, 2010
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Product Specification