DS565 Datasheet, PDF (24/28 Pages) Xilinx, Inc – PLBV46 Master Burst

PLBV46 Master Burst (v1.01a)
Transfer Length Limitations
IP2Bus_Mst_Length(0:11) signal in the Master’s Command Interface qualifiers allows the user to specify a read or
write burst transfer length in bytes (length is ignored for Single data beat commands). The length specified must be
in increments of the Native Data Width of the Master (C_MPLB_DWIDTH/8) and cannot exceed a 12 bit
representation. So the following maximum transfer lengths are allowed:
• C_MPLB_DWIDTH = 32, then maximum length is 4092 bytes (4096 - 4)
• C_MPLB_DWIDTH = 64, then maximum length is 4084 bytes (4096 - 8)
• C_MPLB_DWIDTH = 128, then maximum length is 4080 bytes (4096 - 16)
PLB Burst operations require a minimum of 2 data beats (otherwise Single data beat transfers must be used). Thus,
the minimum transfer length for burst transfers is dependent upon the Native Data Width of the Master. The
following minimum transfer lengths are required:
• C_MPLB_DWIDTH = 32, then minimum length is 8 bytes [(32/8) * 2]
• C_MPLB_DWIDTH = 64, then minimum length is 16 bytes [(64/8) * 2]
• C_MPLB_DWIDTH = 128, then minimum length is 32 bytes [(128/8) * 2]
Considerations for Request Spawning
One important aspect of the Master operation must be kept in mind by the User is the ability of the Master to spawn
multiple child PLB requests when mechanizing a single request from the Client IP. This can occur during burst
requests when the requested transfer length specified by the IP2Bus_Mst_Length qualifier exceeds 16 data beats
times the native byte width of the Master. For a 32-bit Master, this boundary is 64 bytes. Thus, the
Bus2IP_Mst_CmdAck sent by the Master is a result of the completion of the Address Phase of the initial request
posted to the PLB by the Master. Ensuing Address Phases of spawned requests will not have an associated
Bus2IP_Mst_CmdAck reply to the IP Client. It is also possible that an Bus2IP_Mst_Timeout can occur after the
receipt of Bus2IP_Mst_CmdAck if spawned request address is outside of the mapped address range of a PLB Slave.
This would result in a PLB Timeout condition that in an error status assertion on the status signals of the Command
Interface.
LocalLink Interface Considerations when Using PLBV46 Master Burst
Special LocalLink interface requirements are in play with the PLBV46 Master Burst usage. The design does not
utilize FIFOs to isolate the IP Client from the PLB operations. This approach minimizes resource utilization in the
Master but requires the IP Client to adhere to some operational restrictions during LocalLink transfers. The PLBv46
Master Burst ignores the IP2Bus_MstWr_MEM inputs. The user should drive these inputs to logic 0.
PLB Command Hold Off
The Master Burst will not initiate a transfer request onto the PLB until the User IP has the associated LocalLink
interface in the ready state. This hold off will result in the Bus2IP_Mst_CmdAck not being asserted if the User IP
logic does not put the associated LocalLink in the ready state. For a read operation, this means that the
IP2Bus_MstRd_dst_rdy_n signal is asserted, signalling that the IP is ready to receive the read data. For a write, the
IP2Bus_MstWr_src_rdy_n signal must be asserted and the first write data value must be present on the
IP2Bus_MstWr_d(0:n) bus.
DS565 December 14, 2010
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