DS565 Datasheet, PDF (14/28 Pages) Xilinx, Inc – PLBV46 Master Burst

PLBV46 Master Burst (v1.01a)
Single Data Beat Write With Error
Two single beat write cycles are shown in Figure 6. The Master has a Native Data Width of 32 bits and the PLB data
width is 32 bits. For both transfers, a Slave data error is reported and the Master’s MD_Error output is asserted and
held. The first assertion of MD_Error is cleared by the IP2Bus_Mst_Reset input from the IPIC interface. The second
assertion of MD_Error is cleared by the MPLB_Rst input from the PLBV46 interface.
X-Ref Target - Figure 6
0ns
MPLB_Clk
MPLB_Rst
100ns
200ns
300ns
400ns
900ns
1
MD_Error
M_request
M_buslock
M_priority
1
M_MSize[0:1]
0
M_ABus[0:31]
M_BE[0:3]
0011
M_RNW
M_size[0:3]
0
M_type[0:2]
0
M_wrDBus[0:31]
WD0
M_wrBurst
M_rdBurst
0
0
10000004
1111
0
0
WD1
PLB_MaddrAck
PLB_MSsize[0:1]
00
00
PLB_MRearbitrate
PLB_MBusy
PLB_RdDBus[0:31]
PLB_MRdDAck
PLB_MWrDAck
PLB_MWrErr
PLB_MRdErr
PLB_RdBTerm
PLB_WrBTerm
IP2Bus_MstRd_Req
IP2Bus_MstWr_Req
IP2Bus_Mst_Type
IP2Bus_Mst_Addr[0:31]
IP2Bus_Mst_BE[0:3]
IP2Bus_Mst_Length[0:11]
10000002
0011
XXX
10000004
1111
XXX
IP2Bus_Mst_Lock
IP2Bus_Mst_Reset
Bus2IP_Mst_CmdAck
Bus2IP_Mst_Cmplt
Bus2IP_Mst_Error
Bus2IP_Mst_Rearbitrate
Bus2IP_Mst_Cmd_Timeout
IP2Bus_MstWr_d[0:31]
IP2Bus_MstWr_REM[0:3]
IP2Bus_MstWr_sof_n
IP2Bus_MstWr_eof_n
IP2Bus_MstWr_src_rdy_n
IP2Bus_MstWr_src_dsc_n
Bus2IP_MstWr_dst_rdy_n
Bus2IP_MstWr_dst_dsc_n
WD0
1100
WD1
0000
Figure 6: PLB Single Data Beat Write Error Timing
DS565 December 14, 2010
www.xilinx.com
14
Product Specification