DS565 Datasheet, PDF (6/28 Pages) Xilinx, Inc – PLBV46 Master Burst

PLBV46 Master Burst (v1.01a)
Table 1: PLBV46 Master Burst I/O Signal Description
Signal Name
Interface Signal Type Init Status
Description
Bus2IP_MstRd_eof_n
IPIC
O
1
Active low signal indicating the
ending data beat of a Read
LocalLink transfer.
Bus2IP_MstRd_src_rdy_n
IPIC
O
1
Active low signal indicating that the
data value asserted on the
Bus2IP_MstRd_d Bus is valid.
Bus2IP_MstRd_src_dsc_n
IPIC
O
1
Active low signal indicating that the
Read LocalLink Source (Master)
needs to discontinue the transfer.
This will only be asserted if the
Master encounters a PLB Timeout
during the address phase of a
parent or child request to the PLB.
IP2Bus_MstRd_dst_rdy_n
IPIC
I
Active low signal indicating that the
data value asserted on the
Bus2IP_MstRd_d Bus is being
accepted by the LocalLink
destination (User Logic).
IP2Bus_MstRd_dst_dsc_n
IPIC
I
Active low signal indicating that the
Read LocalLink Destination (User
Logic) needs to discontinue the
transfer. This is currently
unsupported in this Master. User
Logic should tie this signal to logic
high.
IPIC Write LocalLink Interface Signals
IP2Bus_MstWr_d(0 to
C_MPLB_NATIVE_DWIDTH-1)
IPIC
I
Write data input from the User
Logic.
IP2Bus_MstWr_REM(0 to
C_REM_WIDTH-1)
IPIC
I
LocalLink Remainder input,
ignored by the PLB Master Burst.
User should tie to logic 0.
IP2Bus_MstWr_sof_n
IPIC
I
Active low signal indicating the
starting data beat of a Write
LocalLink transfer.
IP2Bus_MstWr_eof_n
IPIC
I
Active low signal indicating the
ending data beat of a Write
LocalLink transfer.
IP2Bus_MstWr_src_rdy_n
IPIC
I
Active low signal indicating that the
data value asserted on the
IP2Bus_MstWr_d Bus is valid.
IP2Bus_MstWr_src_dsc_n
IPIC
I
Active low signal indicating that the
Write LocalLink Source (User
Logic) needs to discontinue the
transfer. This is currently
unsupported in this Master. User
Logic should tie this signal to logic
high.
DS565 December 14, 2010
www.xilinx.com
6
Product Specification