DS565 Datasheet, PDF (16/28 Pages) Xilinx, Inc – PLBV46 Master Burst

PLBV46 Master Burst (v1.01a)
Fixed Length Burst Write Operation
A fixed length burst write is shown in Figure 8. The Master has a native data width of 32-bits and the PLB data
width is 32-bits. The burst length is set to 32 (0x20) bytes, which results in eight beats of 32-bit data transferred
across the IPIC and PLB interfaces. The burst is address-aligned to at least a 32-bit word, and, consequently, the
Bust2IP_MstWr_REM is set to 0's. The IP2Bus_Mst_BE port is ignored during bursts. The Bus2IP_MstWr_dst_rdy_n
throttles the incrementing of write data due to delays on the PLB bus.
X-Ref Target - Figure 8
0ns
MPLB_Clk
M_request
M_buslock
M_priority1[0:1]
M_MSize[0:1]
M_ABus[0:31]
M_BE[0:3]
M_RNW
M_size[0:3]
M_type[0:2]
M_wrDBus[0:31]
M_wrBurst
M_rdBurst
PLB_MaddrAck
PLB_MSsize[0:1]
PLB_MRearbitrate
PLB_MBusy
PLB_RdDBus[0:31]
PLB_MRdDAck
PLB_MWrDAck
PLB_MWrErr
PLB_MRdErr
PLB_RdBTerm
PLB_WrBTerm
IP2Bus_MstRd_Req
IP2Bus_MstWr_Req
IP2Bus_Mst_Type
IP2Bus_Mst_Addr[0:31]
IP2Bus_Mst_BE[0:3]
IP2Bus_Mst_Length[0:11]
IP2Bus_Mst_Lock
IP2Bus_Mst_Reset
Bus2IP_Mst_CmdAck
Bus2IP_Mst_Cmplt
Bus2IP_Mst_Error
Bus2IP_Mst_Rearbitrate
Bus2IP_Mst_Cmd_Timeout
Bus2IP_MstRd_d[0:31]
Bus2IP_MstRd_REM[0:3]
Bus2IP_MstRd_sof_n
Bus2IP_MstRd_eof_n
Bus2IP_MstRd_src_rdy_n
Bus2IP_MstRd_src_dsc_n
IP2Bus_MstRd_dst_rdy_n
IP2Bus_MstRd_dst_dsc_n
IP2Bus_MstWr_d[0:31]
IP2Bus_MstWr_REM[0:3]
IP2Bus_MstWr_sof_n
IP2Bus_MstWr_eof_n
IP2Bus_MstWr_src_rdy_n
IP2Bus_MstWr_src_dsc_n
Bus2IP_MstWr_dst_rdy_n
Bus2IP_MstWr_dst_dsc_n
100ns
200ns
300ns
00
0
10000004
1111
0
0
WD0
WD1WD2 Wd3 WD4WD5WD6 WD7
00
10000004
XXXX
020
WD0
0000
WD1
WD2 WD3 WD4 WD5 WD6 WD7
0000
Figure 8: Fixed Length Burst Write Timing
DS565 December 14, 2010
www.xilinx.com
16
Product Specification