DS565 Datasheet, PDF (4/28 Pages) Xilinx, Inc – PLBV46 Master Burst

PLBV46 Master Burst (v1.01a)
I/O Signals
The PLBV46 Master Burst signals are listed and described in the following table.
Table 1: PLBV46 Master Burst I/O Signal Description
Signal Name
Interface Signal Type Init Status
PLB Clock and Reset
MPLB_Clk
PLB Bus
I
MPLB_Rst
PLB Bus
I
Other System Signal
MD_error
PLB Bus
O
0
Description
PLB main bus clock. See Note 1.
PLB main bus reset.See Note 1.
Master Detected Error Status
Output (active high).
PLB Request and Qualifier Signals
M_request
M_priority
M_buslock
M_RNW
M_BE(0:[C_MPLB_DWIDTH/8]-1)
M_Msize(0:1)
M_size(0:3)
M_type(0:2)
M_ABus(0:31)
M_wrBurst
M_rdBurst
M_wrDBus(0:C_MPLB_DWIDTH-1)
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
PLB Bus
O
0
See Note 1.
O
0
See Note 1.
O
0
See Note 1.
O
0
See Note 1.
O
zeros
See Note 1.
O
00
See Note 1.
O
0000
See Note 1.
O
000
See Note 1.
O
zeros
See Note 1.
O
0
See Note 1.
O
0
See Note 1.
O
zeros
See Note 1.
PLB Reply Signals
PLB_MSSize(0:1)
PLB Bus
I
Unused. See Note 2.
PLB_MaddrAck
PLB Bus
I
See Note 1.
PLB_Mrearbitrate
PLB Bus
I
See Note 1.
PLB_MTimeout
PLB Bus
I
See Note 1.
PLB_MRdErr
PLB Bus
I
See Note 1.
PLB_MWrErr
PLB Bus
I
See Note 1.
PLB_MRdDBus(0:C_MPLB_DWIDTH-1) PLB Bus
I
See Note 1.
PLB_MRdDAck
PLB Bus
I
See Note 1.
PLB_MWrDAck
PLB Bus
I
See Note 1.
PLB_RdBTerm
PLB Bus
I
See Note 1.
PLB_MWrBTerm
PLB Bus
I
See Note 1.
PLB Signal Ports Included in the Design but Unused Internally
M_TAttribute(0 to 15)
PLB Bus
O
0
Unused. See Note 2.
DS565 December 14, 2010
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