DS565 Datasheet, PDF (28/28 Pages) Xilinx, Inc – PLBV46 Master Burst

PLBV46 Master Burst (v1.01a)
Reference Documents
The following documents contain reference information important to understanding the PLBV46 Master Burst
design.
1. IBM CoreConnect128-Bit Processor Local Bus, Architectural Specification (v4.6).
2. Xilinx SP026 PLBV46 Interface Simplifications.
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Revision History
Date
9/21/06
01/03/07
7/20/07
01/07/08
4/21/08
5/14/08
12/02/08
5/26/10
6/23/10
12/14/10
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
2.0
Revision
Initial Xilinx release.
Added native data Width options of 64 and 128 bits; added Conversion Cycle and
Burst Length Expansion functionality to supported features
Added SP026 to Reference Documents List; removed Bus Lock as a supported
feature.
Corrected minor issues with various timing diagrams; added additional text in the
User Applications Topics; clarified some Features statements
Added Automotive Spartan-3E, Automotive Spartan-3A, Automotive Spartan-3, and
Automotive Spartan-3A DSP support.
Updates to reflect v1_01_a of the core.
Added clarifications for LocalLink signals and PLBV46 Master Burst usage per
CR478853.
Corrected a signal name in Table 1 from Bus2IP_MstRd_dst_dsc_n to
Bus2IP_MstWr_dst_dsc_n.
Incorporated CR547389; added clarification about the IP2Bus_MstWr_REM not
being used by this core.
Updated to add Virtex-6 and Spartan-6 as supported devices.
Text updates per CR 567030.
DS565 December 14, 2010
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Product Specification