DS565 Datasheet, PDF (23/28 Pages) Xilinx, Inc – PLBV46 Master Burst

PLBV46 Master Burst (v1.01a)
Register Descriptions
The PLBV46 Master Burst has no user accessible registers.
User Application Topics
The Command Interface
The PLBV46 Master Burst is controlled by the Client IP Logic via the command interface. The command interface
provides the mechanism to request a data transfer and the status of the transfer. The actual data transfer is
performed on the Read and Write LocalLink interfaces. The command interface consists of the following:
• Inputs to the Master Service (from IP Client)
• IP2Bus_MstRd_Request (Read Request
• IP2Bus_MstWr_Request (Write Request)
• IP2Bus_Mst_Addr(0:31) (Starting PLB address)
• IP2Bus_Mst_Length(0:11) (Transfer Length limit in bytes)
• IP2Bus_Mst_BE(0:3) (Byte Enable designator for single data beat requests)
• IP2Bus_Mst_Type (specifies single or fixed length burst request)
• IP2Bus_Mst_Lock (PLB Bus Lock qualifier)
• IP2Bus_Mst_Reset (Forces a synchronous reset of the Master logic)
• Status outputs from the Master to the IP Client
• Bus2IP_Mst_CmdAck (Initial request to the PLB has been Command Acknowledge
• Bus2IP_Mst_Cmplt (Command Completion indication)
• Bus2IP_Mst_Error (Command Error)
• Bus2IP_Mst_Rearbitrate (Command PLB Rearbitrate)
• Bus2IP_Mst_Timeout (Request has timed out on the PLB)
The Command Interface protocol requires that the IP Client drive the IP2Bus_MstRd_Request or the
IP2Bus_MstWr_Request and the associated qualifiers until the Bus2IP_Mst_CmdAck is received from the Master.
Upon the receipt of the Bus2IP_Mst_CmdAck, the IP Client must deassert the request and optionally the associated
qualifiers. If a PLB Timeout occurs during the initial PLB Address Phase of a request, the Bus2IP_Mst_CmdAck
assertion will not occur. Instead the Master will reply with the Bus2IP_Mst_Timeout status asserted in conjunction
with assertion of the Bus2IP_Mst_Cmplt status and the Bus2IP_Mst_Error. This is an indication to the IP Client that
the address of the request did not match any assigned address range of a PLB Slave or the type of request was not
support by the target Slave in the system(i.e. A single data beat only Slave will not respond to a burst request). If a
Bus2IP_Mst_CmdAck is asserted by the Master, then the Master has successfully negotiated a PLB Address Phase
with the starting address and command qualifiers and the corresponding data phase is in progress. When the PLB
Data Phase completes, the Master will assert the Bus2IP_Mst_Cmplt signal. If a Data Phase error is received from
the PLB Slave by the Master, the Bus2IP_Mst_Error status will be also be asserted when the Bus2IP_Mst_Cmplt is
asserted. The duration of the Bus2IP_Mst_Cmplt assertion is one PLB clock period.
DS565 December 14, 2010
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Product Specification